llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-sparc Author: Koakuma (koachan) <details> <summary>Changes</summary> --- Full diff: https://github.com/llvm/llvm-project/pull/139451.diff 5 Files Affected: - (modified) llvm/lib/Target/Sparc/Sparc.td (+5-1) - (added) llvm/lib/Target/Sparc/SparcInstrCrypto.td (+98) - (modified) llvm/lib/Target/Sparc/SparcInstrInfo.td (+5) - (added) llvm/test/MC/Disassembler/Sparc/sparc-crypto.txt (+56) - (added) llvm/test/MC/Sparc/sparc-crypto.s (+88) ``````````diff diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td index 6e6c887e60e12..7c26bf9061cb6 100644 --- a/llvm/lib/Target/Sparc/Sparc.td +++ b/llvm/lib/Target/Sparc/Sparc.td @@ -58,6 +58,9 @@ def FeatureUA2007 def FeatureOSA2011 : SubtargetFeature<"osa2011", "IsOSA2011", "true", "Enable Oracle SPARC Architecture 2011 extensions">; +def FeatureCrypto + : SubtargetFeature<"crypto", "IsCrypto", "true", + "Enable cryptographic extensions">; def FeatureLeon : SubtargetFeature<"leon", "IsLeon", "true", "Enable LEON extensions">; @@ -169,7 +172,8 @@ def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc, FeatureUA2005, FeatureUA2007]>; def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc, FeatureVIS, FeatureVIS2, FeatureVIS3, - FeatureUA2005, FeatureUA2007, FeatureOSA2011]>; + FeatureUA2005, FeatureUA2007, FeatureOSA2011, + FeatureCrypto]>; // LEON 2 FT generic def : Processor<"leon2", LEON2Itineraries, diff --git a/llvm/lib/Target/Sparc/SparcInstrCrypto.td b/llvm/lib/Target/Sparc/SparcInstrCrypto.td new file mode 100644 index 0000000000000..0e7063f99eb06 --- /dev/null +++ b/llvm/lib/Target/Sparc/SparcInstrCrypto.td @@ -0,0 +1,98 @@ +//===----------- SparcInstrCrypto.td - cryptographic extensions -----------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains instruction formats, definitions and patterns needed for +// cryptographic instructions on SPARC. +//===----------------------------------------------------------------------===// + + +// Convenience template for 4-operand instructions +class FourOpImm<string OpcStr, bits<6> op3val, bits<4> op5val, + RegisterClass RC> + : F3_4<op3val, op5val, (outs RC:$rd), (ins RC:$rs1, RC:$rs2, simm5Op:$rs3), + !strconcat(OpcStr, " $rs1, $rs2, $rs3, $rd")>; + +let Predicates = [HasCrypto] in { +def AES_EROUND01 : FourOp<"aes_eround01", 0b011001, 0b0000, DFPRegs>; +def AES_EROUND23 : FourOp<"aes_eround23", 0b011001, 0b0001, DFPRegs>; +def AES_DROUND01 : FourOp<"aes_dround01", 0b011001, 0b0010, DFPRegs>; +def AES_DROUND23 : FourOp<"aes_dround23", 0b011001, 0b0011, DFPRegs>; +def AES_EROUND01_LAST : FourOp<"aes_eround01_l", 0b011001, 0b0100, DFPRegs>; +def AES_EROUND23_LAST : FourOp<"aes_eround23_l", 0b011001, 0b0101, DFPRegs>; +def AES_DROUND01_LAST : FourOp<"aes_dround01_l", 0b011001, 0b0110, DFPRegs>; +def AES_DROUND23_LAST : FourOp<"aes_dround23_l", 0b011001, 0b0111, DFPRegs>; +def AES_KEXPAND0 : F3_3<2, 0b110110, 0b100110000, + (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), + "aes_kexpand0 $rs1, $rs2, $rd", []>; +def AES_KEXPAND1 : FourOpImm<"aes_kexpand1", 0b011001, 0b1000, DFPRegs>; +def AES_KEXPAND2 : F3_3<2, 0b110110, 0b100110001, + (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), + "aes_kexpand2 $rs1, $rs2, $rd", []>; + +def CAMELLIA_F : FourOp<"camellia_f", 0b011001, 0b1100, DFPRegs>; +def CAMELLIA_FL : F3_3<2, 0b110110, 0b100111100, + (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), + "camellia_fl $rs1, $rs2, $rd", []>; +def CAMELLIA_FLI : F3_3<2, 0b110110, 0b100111101, + (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), + "camellia_fli $rs1, $rs2, $rd", []>; + +def CRC32C : F3_3<2, 0b110110, 0b101000111, + (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), + "crc32c $rs1, $rs2, $rd", []>; + +def DES_ROUND : FourOp<"des_round", 0b011001, 0b1001, DFPRegs>; +let rs2 = 0 in { +def DES_IP : F3_3<2, 0b110110, 0b100110100, + (outs DFPRegs:$rd), (ins DFPRegs:$rs1), + "des_ip $rs1, $rd", []>; +def DES_IIP : F3_3<2, 0b110110, 0b100110101, + (outs DFPRegs:$rd), (ins DFPRegs:$rs1), + "des_iip $rs1, $rd", []>; +} +def DES_KEXPAND : F3_3<2, 0b110110, 0b100110110, + (outs DFPRegs:$rd), (ins DFPRegs:$rs1, simm5Op:$rs2), + "des_kexpand $rs1, $rs2, $rd", []>; + +let rs1 = 0, rs2 = 0, rd = 0 in { +let Uses = [D0, D1, D2, D5, D6, D7, D8, D9, D10, D11], + Defs = [D0, D1, D2, D3, D4, D5, D6, D7] in +def MD5 : F3_3<2, 0b110110, 0b101000000, (outs), (ins), "md5", []>; +let Uses = [D0, D1, D2, D4, D5, D6, D7, D8, D9, D10, D11], + Defs = [D0, D1, D2] in +def SHA1 : F3_3<2, 0b110110, 0b101000001, (outs), (ins), "sha1", []>; +let Uses = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11], + Defs = [D0, D1, D2, D3] in +def SHA256 : F3_3<2, 0b110110, 0b101000010, (outs), (ins), "sha256", []>; +let Uses = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, + D12, D13, D14, D15, D16, D17, D18, D19, D20, D21, D22, D23], + Defs = [D0, D1, D2, D3, D4, D5, D6, D7] in +def SHA512 : F3_3<2, 0b110110, 0b101000011, (outs), (ins), "sha512", []>; +} + +// These instructions use and clobber all DFP and non-reserved Int registers. +let rs1 = 0, rd = 0, +Uses = [ D0, D1, D2, D3, D4, D5, D6, D7, + D8, D9, D10, D11, D12, D13, D14, D15, + D16, D17, D18, D19, D20, D21, D22, D23, + D24, D25, D26, D27, D28, D29, D30, D31, + O0, O1, O2, O3, O4, O5, + L0, L1, L2, L3, L4, L5, L6, L7, + I0, I1, I2, I3, I4, I5 ], +Defs = [ D0, D1, D2, D3, D4, D5, D6, D7, + D8, D9, D10, D11, D12, D13, D14, D15, + D16, D17, D18, D19, D20, D21, D22, D23, + D24, D25, D26, D27, D28, D29, D30, D31, + O0, O1, O2, O3, O4, O5, + L0, L1, L2, L3, L4, L5, L6, L7, + I0, I1, I2, I3, I4, I5 ] in { +def MPMUL : F3_3<2, 0b110110, 0b101001000, (outs), (ins simm5Op:$rs2), "mpmul $rs2", []>; +def MONTMUL : F3_3<2, 0b110110, 0b101001001, (outs), (ins simm5Op:$rs2), "montmul $rs2", []>; +def MONTSQR : F3_3<2, 0b110110, 0b101001010, (outs), (ins simm5Op:$rs2), "montsqr $rs2", []>; +} +} // Predicates = [HasCrypto] diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td index c14d72b33c08c..b0c09eefc97fb 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.td +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -59,6 +59,10 @@ def HasUA2007 : Predicate<"Subtarget->isUA2007()">, def HasOSA2011 : Predicate<"Subtarget->isOSA2011()">, AssemblerPredicate<(all_of FeatureOSA2011)>; +// HasCrypto - This is true when the target processor has cryptographic extensions. +def HasCrypto : Predicate<"Subtarget->isCrypto()">, + AssemblerPredicate<(all_of FeatureCrypto)>; + // HasHardQuad - This is true when the target processor supports quad floating // point instructions. def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">; @@ -1993,4 +1997,5 @@ def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)), include "SparcInstr64Bit.td" include "SparcInstrVIS.td" include "SparcInstrUAOSA.td" +include "SparcInstrCrypto.td" include "SparcInstrAliases.td" diff --git a/llvm/test/MC/Disassembler/Sparc/sparc-crypto.txt b/llvm/test/MC/Disassembler/Sparc/sparc-crypto.txt new file mode 100644 index 0000000000000..ceae8b4ce695c --- /dev/null +++ b/llvm/test/MC/Disassembler/Sparc/sparc-crypto.txt @@ -0,0 +1,56 @@ +# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux -mattr=+crypto | FileCheck %s + +## Crypto instructions. + +# CHECK: aes_eround01 %f0, %f2, %f4, %f6 +0x8c,0xc8,0x08,0x02 +# CHECK: aes_eround23 %f0, %f2, %f4, %f6 +0x8c,0xc8,0x08,0x22 +# CHECK: aes_dround01 %f0, %f2, %f4, %f6 +0x8c,0xc8,0x08,0x42 +# CHECK: aes_dround23 %f0, %f2, %f4, %f6 +0x8c,0xc8,0x08,0x62 +# CHECK: aes_eround01_l %f0, %f2, %f4, %f6 +0x8c,0xc8,0x08,0x82 +# CHECK: aes_eround23_l %f0, %f2, %f4, %f6 +0x8c,0xc8,0x08,0xa2 +# CHECK: aes_dround01_l %f0, %f2, %f4, %f6 +0x8c,0xc8,0x08,0xc2 +# CHECK: aes_dround23_l %f0, %f2, %f4, %f6 +0x8c,0xc8,0x08,0xe2 +# CHECK: aes_kexpand0 %f0, %f2, %f4 +0x89,0xb0,0x26,0x02 +# CHECK: aes_kexpand1 %f0, %f2, 4, %f6 +0x8c,0xc8,0x09,0x02 +# CHECK: aes_kexpand2 %f0, %f2, %f4 +0x89,0xb0,0x26,0x22 +# CHECK: camellia_f %f0, %f2, %f4, %f6 +0x8c,0xc8,0x09,0x82 +# CHECK: camellia_fl %f0, %f2, %f4 +0x89,0xb0,0x27,0x82 +# CHECK: camellia_fli %f0, %f2, %f4 +0x89,0xb0,0x27,0xa2 +# CHECK: crc32c %f0, %f2, %f4 +0x89,0xb0,0x28,0xe2 +# CHECK: des_round %f0, %f2, %f4, %f6 +0x8c,0xc8,0x09,0x22 +# CHECK: des_ip %f0, %f2 +0x85,0xb0,0x26,0x80 +# CHECK: des_iip %f0, %f2 +0x85,0xb0,0x26,0xa0 +# CHECK: des_kexpand %f0, 2, %f4 +0x89,0xb0,0x26,0xc2 +# CHECK: md5 +0x81,0xb0,0x28,0x00 +# CHECK: sha1 +0x81,0xb0,0x28,0x20 +# CHECK: sha256 +0x81,0xb0,0x28,0x40 +# CHECK: sha512 +0x81,0xb0,0x28,0x60 +# CHECK: mpmul 1 +0x81,0xb0,0x29,0x01 +# CHECK: montmul 2 +0x81,0xb0,0x29,0x22 +# CHECK: montsqr 3 +0x81,0xb0,0x29,0x43 diff --git a/llvm/test/MC/Sparc/sparc-crypto.s b/llvm/test/MC/Sparc/sparc-crypto.s new file mode 100644 index 0000000000000..1c6071178eaae --- /dev/null +++ b/llvm/test/MC/Sparc/sparc-crypto.s @@ -0,0 +1,88 @@ +! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-CRYPTO --implicit-check-not=error: +! RUN: llvm-mc %s -triple=sparcv9 -mattr=+crypto -show-encoding | FileCheck %s --check-prefixes=CRYPTO + +!! Crypto instructions. + +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: aes_eround01 %f0, %f2, %f4, %f6 ! encoding: [0x8c,0xc8,0x08,0x02] +aes_eround01 %f0, %f2, %f4, %f6 +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: aes_eround23 %f0, %f2, %f4, %f6 ! encoding: [0x8c,0xc8,0x08,0x22] +aes_eround23 %f0, %f2, %f4, %f6 +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: aes_dround01 %f0, %f2, %f4, %f6 ! encoding: [0x8c,0xc8,0x08,0x42] +aes_dround01 %f0, %f2, %f4, %f6 +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: aes_dround23 %f0, %f2, %f4, %f6 ! encoding: [0x8c,0xc8,0x08,0x62] +aes_dround23 %f0, %f2, %f4, %f6 +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: aes_eround01_l %f0, %f2, %f4, %f6 ! encoding: [0x8c,0xc8,0x08,0x82] +aes_eround01_l %f0, %f2, %f4, %f6 +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: aes_eround23_l %f0, %f2, %f4, %f6 ! encoding: [0x8c,0xc8,0x08,0xa2] +aes_eround23_l %f0, %f2, %f4, %f6 +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: aes_dround01_l %f0, %f2, %f4, %f6 ! encoding: [0x8c,0xc8,0x08,0xc2] +aes_dround01_l %f0, %f2, %f4, %f6 +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: aes_dround23_l %f0, %f2, %f4, %f6 ! encoding: [0x8c,0xc8,0x08,0xe2] +aes_dround23_l %f0, %f2, %f4, %f6 +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: aes_kexpand0 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x26,0x02] +aes_kexpand0 %f0, %f2, %f4 +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: aes_kexpand1 %f0, %f2, 4, %f6 ! encoding: [0x8c,0xc8,0x09,0x02] +aes_kexpand1 %f0, %f2, 4, %f6 +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: aes_kexpand2 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x26,0x22] +aes_kexpand2 %f0, %f2, %f4 + +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: camellia_f %f0, %f2, %f4, %f6 ! encoding: [0x8c,0xc8,0x09,0x82] +camellia_f %f0, %f2, %f4, %f6 +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: camellia_fl %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x27,0x82] +camellia_fl %f0, %f2, %f4 +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: camellia_fli %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x27,0xa2] +camellia_fli %f0, %f2, %f4 + +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: crc32c %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x28,0xe2] +crc32c %f0, %f2, %f4 + +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: des_round %f0, %f2, %f4, %f6 ! encoding: [0x8c,0xc8,0x09,0x22] +des_round %f0, %f2, %f4, %f6 +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: des_ip %f0, %f2 ! encoding: [0x85,0xb0,0x26,0x80] +des_ip %f0, %f2 +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: des_iip %f0, %f2 ! encoding: [0x85,0xb0,0x26,0xa0] +des_iip %f0, %f2 +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: des_kexpand %f0, 2, %f4 ! encoding: [0x89,0xb0,0x26,0xc2] +des_kexpand %f0, 2, %f4 + +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: md5 ! encoding: [0x81,0xb0,0x28,0x00] +md5 +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: sha1 ! encoding: [0x81,0xb0,0x28,0x20] +sha1 +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: sha256 ! encoding: [0x81,0xb0,0x28,0x40] +sha256 +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: sha512 ! encoding: [0x81,0xb0,0x28,0x60] +sha512 + +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: mpmul 1 ! encoding: [0x81,0xb0,0x29,0x01] +mpmul 1 +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: montmul 2 ! encoding: [0x81,0xb0,0x29,0x22] +montmul 2 +! NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +! CRYPTO: montsqr 3 ! encoding: [0x81,0xb0,0x29,0x43] +montsqr 3 `````````` </details> https://github.com/llvm/llvm-project/pull/139451 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
