llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: Iris Shi (el-ev) <details> <summary>Changes</summary> --- Patch is 24.97 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/139495.diff 14 Files Affected: - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoQ.td (+61-39) - (modified) llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td (+1) - (modified) llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td (+1) - (modified) llvm/lib/Target/RISCV/RISCVSchedRocket.td (+1) - (modified) llvm/lib/Target/RISCV/RISCVSchedSiFive7.td (+1) - (modified) llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td (+1) - (modified) llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td (+1) - (modified) llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td (+1) - (modified) llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td (+1) - (modified) llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td (+1) - (modified) llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td (+1) - (modified) llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td (+1) - (modified) llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td (+1) - (modified) llvm/lib/Target/RISCV/RISCVSchedule.td (+85-3) ``````````diff diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td index 7d216b5dd87c0..8cc965ccc515d 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td @@ -25,97 +25,119 @@ defvar QExtsRV64 = [QExt]; //===----------------------------------------------------------------------===// let Predicates = [HasStdExtQ] in { - // def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>; - let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in - def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd), - (ins GPRMem:$rs1, simm12:$imm12), - "flq", "$rd, ${imm12}(${rs1})">; + def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>; + // Operands for stores are in the order srcreg, base, offset rather than // reflecting the order these fields are specified in the instruction // encoding. - // def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>; - let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in - def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs), - (ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12), - "fsq", "$rs2, ${imm12}(${rs1})">; + def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>; } // Predicates = [HasStdExtQ] foreach Ext = QExts in { - defm FMADD_Q : FPFMA_rrr_frm_m<OPC_MADD, 0b11, "fmadd.q", Ext>; - defm FMSUB_Q : FPFMA_rrr_frm_m<OPC_MSUB, 0b11, "fmsub.q", Ext>; - defm FNMSUB_Q : FPFMA_rrr_frm_m<OPC_NMSUB, 0b11, "fnmsub.q", Ext>; - defm FNMADD_Q : FPFMA_rrr_frm_m<OPC_NMADD, 0b11, "fnmadd.q", Ext>; + let SchedRW = [WriteFMA128, ReadFMA128, ReadFMA128, ReadFMA128Addend] in { + defm FMADD_Q : FPFMA_rrr_frm_m<OPC_MADD, 0b11, "fmadd.q", Ext>; + defm FMSUB_Q : FPFMA_rrr_frm_m<OPC_MSUB, 0b11, "fmsub.q", Ext>; + defm FNMSUB_Q : FPFMA_rrr_frm_m<OPC_NMSUB, 0b11, "fnmsub.q", Ext>; + defm FNMADD_Q : FPFMA_rrr_frm_m<OPC_NMADD, 0b11, "fnmadd.q", Ext>; + } - defm FADD_Q : FPALU_rr_frm_m<0b0000011, "fadd.q", Ext>; - defm FSUB_Q : FPALU_rr_frm_m<0b0000111, "fsub.q", Ext>; + let SchedRW = [WriteFAdd128, ReadFAdd128, ReadFAdd128] in { + defm FADD_Q : FPALU_rr_frm_m<0b0000011, "fadd.q", Ext>; + defm FSUB_Q : FPALU_rr_frm_m<0b0000111, "fsub.q", Ext>; + } + let SchedRW = [WriteFMul128, ReadFMul128, ReadFMul128] in defm FMUL_Q : FPALU_rr_frm_m<0b0001011, "fmul.q", Ext>; + let SchedRW = [WriteFDiv128, ReadFDiv128, ReadFDiv128] in defm FDIV_Q : FPALU_rr_frm_m<0b0001111, "fdiv.q", Ext>; defm FSQRT_Q : FPUnaryOp_r_frm_m<0b0101111, 0b00000, Ext, Ext.PrimaryTy, - Ext.PrimaryTy, "fsqrt.q">; + Ext.PrimaryTy, "fsqrt.q">, + Sched<[WriteFSqrt128, ReadFSqrt128]>; - let mayRaiseFPException = 0 in { + let SchedRW = [WriteFSGNJ128, ReadFSGNJ128, ReadFSGNJ128], + mayRaiseFPException = 0 in { defm FSGNJ_Q : FPALU_rr_m<0b0010011, 0b000, "fsgnj.q", Ext>; defm FSGNJN_Q : FPALU_rr_m<0b0010011, 0b001, "fsgnjn.q", Ext>; defm FSGNJX_Q : FPALU_rr_m<0b0010011, 0b010, "fsgnjx.q", Ext>; } - defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>; - defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>; + let SchedRW = [WriteFMinMax128, ReadFMinMax128, ReadFMinMax128] in { + defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>; + defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>; + } defm FCVT_S_Q : FPUnaryOp_r_frm_m<0b0100000, 0b00011, Ext, Ext.F32Ty, - Ext.PrimaryTy, "fcvt.s.q">; + Ext.PrimaryTy, "fcvt.s.q">, + Sched<[WriteFCvtF128ToF32, ReadFCvtF128ToF32]>; defm FCVT_Q_S : FPUnaryOp_r_frmlegacy_m<0b0100011, 0b00000, Ext, - Ext.PrimaryTy, Ext.F32Ty, "fcvt.q.s">; + Ext.PrimaryTy, Ext.F32Ty, + "fcvt.q.s">, + Sched<[WriteFCvtF32ToF128, ReadFCvtF32ToF128]>; defm FCVT_D_Q : FPUnaryOp_r_frm_m<0b0100001, 0b00011, Ext, Ext.F64Ty, - Ext.PrimaryTy, "fcvt.d.q">; + Ext.PrimaryTy, "fcvt.d.q">, + Sched<[WriteFCvtF128ToF64, ReadFCvtF128ToF64]>; defm FCVT_Q_D : FPUnaryOp_r_frmlegacy_m<0b0100011, 0b00001, Ext, - Ext.PrimaryTy, Ext.F64Ty, "fcvt.q.d">; - - defm FEQ_Q : FPCmp_rr_m<0b1010011, 0b010, "feq.q", Ext, Commutable = 1>; - defm FLT_Q : FPCmp_rr_m<0b1010011, 0b001, "flt.q", Ext>; - defm FLE_Q : FPCmp_rr_m<0b1010011, 0b000, "fle.q", Ext>; + Ext.PrimaryTy, Ext.F64Ty, + "fcvt.q.d">, + Sched<[WriteFCvtF64ToF128, ReadFCvtF64ToF128]>; + + let SchedRW = [WriteFCmp128, ReadFCmp128, ReadFCmp128] in { + defm FEQ_Q : FPCmp_rr_m<0b1010011, 0b010, "feq.q", Ext, Commutable = 1>; + defm FLT_Q : FPCmp_rr_m<0b1010011, 0b001, "flt.q", Ext>; + defm FLE_Q : FPCmp_rr_m<0b1010011, 0b000, "fle.q", Ext>; + } let mayRaiseFPException = 0 in defm FCLASS_Q : FPUnaryOp_r_m<0b1110011, 0b00000, 0b001, Ext, GPR, - Ext.PrimaryTy, "fclass.q">; + Ext.PrimaryTy, "fclass.q">, + Sched<[WriteFClass128, ReadFClass128]>; let IsSignExtendingOpW = 1 in defm FCVT_W_Q : FPUnaryOp_r_frm_m<0b1100011, 0b00000, Ext, GPR, - Ext.PrimaryTy, "fcvt.w.q">; + Ext.PrimaryTy, "fcvt.w.q">, + Sched<[WriteFCvtF128ToI32, ReadFCvtF128ToI32]>; let IsSignExtendingOpW = 1 in defm FCVT_WU_Q : FPUnaryOp_r_frm_m<0b1100011, 0b00001, Ext, GPR, - Ext.PrimaryTy, "fcvt.wu.q">; + Ext.PrimaryTy, "fcvt.wu.q">, + Sched<[WriteFCvtF128ToI32, ReadFCvtF128ToI32]>; let mayRaiseFPException = 0 in defm FCVT_Q_W : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00000, Ext, - Ext.PrimaryTy, GPR, "fcvt.q.w">; + Ext.PrimaryTy, GPR, "fcvt.q.w">, + Sched<[WriteFCvtI32ToF128, ReadFCvtI32ToF128]>; let mayRaiseFPException = 0 in defm FCVT_Q_WU : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00001, Ext, - Ext.PrimaryTy, GPR, "fcvt.q.wu">; + Ext.PrimaryTy, GPR, "fcvt.q.wu">, + Sched<[WriteFCvtI32ToF128, ReadFCvtI32ToF128]>; } // foreach Ext = QExts foreach Ext = QExtsRV64 in { defm FCVT_L_Q : FPUnaryOp_r_frm_m<0b1100011, 0b00010, Ext, GPR, - Ext.PrimaryTy, "fcvt.l.q", [IsRV64]>; + Ext.PrimaryTy, "fcvt.l.q", [IsRV64]>, + Sched<[WriteFCvtF128ToI64, ReadFCvtF128ToI64]>; defm FCVT_LU_Q : FPUnaryOp_r_frm_m<0b1100011, 0b00011, Ext, GPR, - Ext.PrimaryTy, "fcvt.lu.q", [IsRV64]>; + Ext.PrimaryTy, "fcvt.lu.q", [IsRV64]>, + Sched<[WriteFCvtF128ToI64, ReadFCvtF128ToI64]>; let mayRaiseFPException = 0 in - defm FCVT_Q_L : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00010, Ext, Ext.PrimaryTy, - GPR, "fcvt.q.l", [IsRV64]>; + defm FCVT_Q_L : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00010, Ext, + Ext.PrimaryTy, GPR, "fcvt.q.l", + [IsRV64]>, + Sched<[WriteFCvtI64ToF128, ReadFCvtI64ToF128]>; let mayRaiseFPException = 0 in - defm FCVT_Q_LU : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00011, Ext, Ext.PrimaryTy, - GPR, "fcvt.q.lu", [IsRV64]>; + defm FCVT_Q_LU : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00011, Ext, + Ext.PrimaryTy, GPR, "fcvt.q.lu", + [IsRV64]>, + Sched<[WriteFCvtI64ToF128, ReadFCvtI64ToF128]>; } // foreach Ext = QExtsRV64 //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td b/llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td index be9c4ddf7cf48..248d2273ef2f4 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td +++ b/llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td @@ -492,6 +492,7 @@ def : ReadAdvance<ReadFSqrt16, 0>; //===----------------------------------------------------------------------===// // Unsupported extensions //===----------------------------------------------------------------------===// +defm : UnsupportedSchedQ; defm : UnsupportedSchedV; defm : UnsupportedSchedZvk; defm : UnsupportedSchedSFB; diff --git a/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td b/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td index a1127966e8417..8ba4cd0acdd6c 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td +++ b/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td @@ -263,6 +263,7 @@ def : ReadAdvance<ReadIRem, 0>; def : ReadAdvance<ReadIRem32, 0>; // Unsupported extensions. +defm : UnsupportedSchedQ; defm : UnsupportedSchedV; defm : UnsupportedSchedZbc; defm : UnsupportedSchedZbs; diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td index 1148581415380..4c4654ba2fc0f 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td +++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td @@ -250,6 +250,7 @@ def : ReadAdvance<ReadFClass64, 0>; //===----------------------------------------------------------------------===// // Unsupported extensions +defm : UnsupportedSchedQ; defm : UnsupportedSchedV; defm : UnsupportedSchedZabha; defm : UnsupportedSchedZba; diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td index f4d2073d3b52d..af64a871a9292 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td @@ -1300,6 +1300,7 @@ foreach mx = SchedMxList in { //===----------------------------------------------------------------------===// // Unsupported extensions +defm : UnsupportedSchedQ; defm : UnsupportedSchedZabha; defm : UnsupportedSchedZbc; defm : UnsupportedSchedZbkb; diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td index 1ac05c9444725..370ea64699383 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td @@ -1231,6 +1231,7 @@ defm "" : LMULReadAdvance<"ReadVSM3MEV", 0>; //===----------------------------------------------------------------------===// // Unsupported extensions +defm : UnsupportedSchedQ; defm : UnsupportedSchedZabha; defm : UnsupportedSchedZbc; defm : UnsupportedSchedZbkb; diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td index ca116e0c54f3f..5933d73174f79 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td @@ -348,6 +348,7 @@ def : ReadAdvance<ReadSHXADD32, 0>; //===----------------------------------------------------------------------===// // Unsupported extensions +defm : UnsupportedSchedQ; defm : UnsupportedSchedV; defm : UnsupportedSchedZabha; defm : UnsupportedSchedZbc; diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td index 2bfd5ef811c7b..7c04d1c54473d 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td @@ -1487,6 +1487,7 @@ defm "" : LMULReadAdvance<"ReadVSM3MEV", 0>; //===----------------------------------------------------------------------===// // Unsupported extensions +defm : UnsupportedSchedQ; defm : UnsupportedSchedZabha; defm : UnsupportedSchedZbc; defm : UnsupportedSchedZbkb; diff --git a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td index c21ab969d12ac..8948694c420a0 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td @@ -342,6 +342,7 @@ def : ReadAdvance<ReadSingleBitImm, 0>; //===----------------------------------------------------------------------===// // Unsupported extensions +defm : UnsupportedSchedQ; defm : UnsupportedSchedV; defm : UnsupportedSchedXsfvcp; defm : UnsupportedSchedZabha; diff --git a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td index e509abc9f922e..815c2da992a11 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td @@ -199,6 +199,7 @@ multiclass SCR3_Unsupported : multiclass SCR4_SCR5_Unsupported : SCR_Unsupported, + UnsupportedSchedQ, UnsupportedSchedZfhmin; // Bypasses (none) diff --git a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td index 4631474a945cb..decd578360753 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td @@ -241,6 +241,7 @@ multiclass SCR7_Other { // Unsupported scheduling classes for SCR7. multiclass SCR7_Unsupported { + defm : UnsupportedSchedQ; defm : UnsupportedSchedSFB; defm : UnsupportedSchedV; defm : UnsupportedSchedXsfvcp; diff --git a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td index 2afe02552974e..5322de100d0ad 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td +++ b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td @@ -318,6 +318,7 @@ def : ReadAdvance<ReadSingleBitImm, 0>; //===----------------------------------------------------------------------===// // Unsupported extensions +defm : UnsupportedSchedQ; defm : UnsupportedSchedV; defm : UnsupportedSchedXsfvcp; defm : UnsupportedSchedZabha; diff --git a/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td b/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td index 16d192feafd29..3076a2ebb813d 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td +++ b/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td @@ -306,6 +306,7 @@ def : ReadAdvance<ReadXPERM, 0>; //===----------------------------------------------------------------------===// // Unsupported extensions +defm : UnsupportedSchedQ; defm : UnsupportedSchedV; defm : UnsupportedSchedZfa; defm : UnsupportedSchedZfhmin; diff --git a/llvm/lib/Target/RISCV/RISCVSchedule.td b/llvm/lib/Target/RISCV/RISCVSchedule.td index ceaeb85d421ff..c8b0f0c9325f7 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedule.td +++ b/llvm/lib/Target/RISCV/RISCVSchedule.td @@ -43,34 +43,43 @@ def WriteAtomicSTD : SchedWrite; // Atomic store double word def WriteFAdd16 : SchedWrite; // 16-bit floating point addition/subtraction def WriteFAdd32 : SchedWrite; // 32-bit floating point addition/subtraction def WriteFAdd64 : SchedWrite; // 64-bit floating point addition/subtraction +def WriteFAdd128 : SchedWrite; // 128-bit floating point addition/subtraction def WriteFMul16 : SchedWrite; // 16-bit floating point multiply def WriteFMul32 : SchedWrite; // 32-bit floating point multiply def WriteFMul64 : SchedWrite; // 64-bit floating point multiply +def WriteFMul128 : SchedWrite; // 128-bit floating point multiply def WriteFMA16 : SchedWrite; // 16-bit floating point fused multiply-add def WriteFMA32 : SchedWrite; // 32-bit floating point fused multiply-add def WriteFMA64 : SchedWrite; // 64-bit floating point fused multiply-add +def WriteFMA128 : SchedWrite; // 128-bit floating point fused multiply-add def WriteFDiv16 : SchedWrite; // 16-bit floating point divide def WriteFDiv32 : SchedWrite; // 32-bit floating point divide def WriteFDiv64 : SchedWrite; // 64-bit floating point divide +def WriteFDiv128 : SchedWrite; // 128-bit floating point divide def WriteFSqrt16 : SchedWrite; // 16-bit floating point sqrt def WriteFSqrt32 : SchedWrite; // 32-bit floating point sqrt def WriteFSqrt64 : SchedWrite; // 64-bit floating point sqrt +def WriteFSqrt128 : SchedWrite; // 128-bit floating point sqrt // Integer to float conversions def WriteFCvtI32ToF16 : SchedWrite; def WriteFCvtI32ToF32 : SchedWrite; def WriteFCvtI32ToF64 : SchedWrite; +def WriteFCvtI32ToF128 : SchedWrite; def WriteFCvtI64ToF16 : SchedWrite; // RV64I only def WriteFCvtI64ToF32 : SchedWrite; // RV64I only def WriteFCvtI64ToF64 : SchedWrite; // RV64I only +def WriteFCvtI64ToF128 : SchedWrite; // RV64I only -//Float to integer conversions +// Float to integer conversions def WriteFCvtF16ToI32 : SchedWrite; def WriteFCvtF16ToI64 : SchedWrite; // RV64I only def WriteFCvtF32ToI32 : SchedWrite; def WriteFCvtF32ToI64 : SchedWrite; // RV64I only def WriteFCvtF64ToI32 : SchedWrite; def WriteFCvtF64ToI64 : SchedWrite; // RV64I only +def WriteFCvtF128ToI32 : SchedWrite; +def WriteFCvtF128ToI64 : SchedWrite; // RV64I only // Float to float conversions def WriteFCvtF32ToF64 : SchedWrite; @@ -79,8 +88,12 @@ def WriteFCvtF16ToF32 : SchedWrite; def WriteFCvtF32ToF16 : SchedWrite; def WriteFCvtF16ToF64 : SchedWrite; def WriteFCvtF64ToF16 : SchedWrite; +def WriteFCvtF128ToF32 : SchedWrite; +def WriteFCvtF128ToF64 : SchedWrite; +def WriteFCvtF32ToF128 : SchedWrite; +def WriteFCvtF64ToF128 : SchedWrite; -// Zfa found instructions. +// Zfa fround instructions. def WriteFRoundF32 : SchedWrite; def WriteFRoundF64 : SchedWrite; def WriteFRoundF16 : SchedWrite; @@ -88,15 +101,19 @@ def WriteFRoundF16 : SchedWrite; def WriteFClass16 : SchedWrite; // 16-bit floating point classify def WriteFClass32 : SchedWrite; // 32-bit floating point classify def WriteFClass64 : SchedWrite; // 64-bit floating point classify +def WriteFClass128 : SchedWrite; // 128-bit floating point classify def WriteFCmp16 : SchedWrite; // 16-bit floating point compare def WriteFCmp32 : SchedWrite; // 32-bit floating point compare def WriteFCmp64 : SchedWrite; // 64-bit floating point compare +def WriteFCmp128 : SchedWrite; // 128-bit floating point compare def WriteFSGNJ16 : SchedWrite; // 16-bit floating point sign-injection def WriteFSGNJ32 : SchedWrite; // 32-bit floating point sign-injection def WriteFSGNJ64 : SchedWrite; // 64-bit floating point sign-injection +def WriteFSGNJ128 : SchedWrite; // 128-bit floating point sign-injection def WriteFMinMax16 : SchedWrite; // 16-bit floating point min or max def WriteFMinMax32 : SchedWrite; // 32-bit floating point min or max def WriteFMinMax64 : SchedWrite; // 64-bit floating point min or max +def WriteFMinMax128 : SchedWrite; // 128-bit floating point min or max def WriteFMovF16ToI16 : SchedWrite; def WriteFMovI16ToF16 : SchedWrite; @@ -112,9 +129,11 @@ def WriteFLI64 : SchedWrite; // Floating point constant load def WriteFLD16 : SchedWrite; // Floating point sp load def WriteFLD32 : SchedWrite; // Floating point sp load def WriteFLD64 : SchedWrite; // Floating point dp load +def WriteFLD128 : SchedWrite; // Floating point qp load def WriteFST16 : SchedWrite; // Floating point sp store def WriteFST32 : SchedWrite; // Floating point sp store def WriteFST64 : SchedWrite; // Floating point dp store +def WriteFST128 : SchedWrite; // Floating point qp store // short forward branch for Bullet def WriteSFB : SchedWrite; @@ -156,42 +175,55 @@ def ReadAtomicSTD : SchedRead; // Atomic store double word def ReadFAdd16 : SchedRead; // 16-bit floating point addition/subtraction def ReadFAdd32 : SchedRead; // 32-bit floating point addition/subtraction def ReadFAdd64 : SchedRead; // 64-bit floating point addition/subtraction +def ReadFAdd128 : SchedRead; // 128-bit floating point addition/subtraction def ReadFMul16 : SchedRead; // 16-bit floating point... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/139495 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
