llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-aarch64 Author: David Green (davemgreen) <details> <summary>Changes</summary> --- Full diff: https://github.com/llvm/llvm-project/pull/139503.diff 4 Files Affected: - (modified) llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp (+10) - (modified) llvm/test/CodeGen/AArch64/aarch64-smull.ll (+12-55) - (modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir (+1-2) - (modified) llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll (+1-2) ``````````diff diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp index 21990be21bbf7..41e36e1e6640b 100644 --- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp +++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp @@ -864,6 +864,16 @@ unsigned GISelValueTracking::computeNumSignBits(Register R, return TyBits - 1; // Every always-zero bit is a sign bit. break; } + case TargetOpcode::G_ASHR: { + Register Src1 = MI.getOperand(1).getReg(); + Register Src2 = MI.getOperand(2).getReg(); + LLT SrcTy = MRI.getType(Src1); + FirstAnswer = computeNumSignBits(Src1, DemandedElts, Depth + 1); + if (auto C = getIConstantSplatVal(Src2, MRI)) + FirstAnswer = std::max<uint64_t>(FirstAnswer + C->getZExtValue(), + SrcTy.getScalarSizeInBits()); + break; + } case TargetOpcode::G_INTRINSIC: case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: case TargetOpcode::G_INTRINSIC_CONVERGENT: diff --git a/llvm/test/CodeGen/AArch64/aarch64-smull.ll b/llvm/test/CodeGen/AArch64/aarch64-smull.ll index 951001c84aed0..591bc65bf3226 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-smull.ll +++ b/llvm/test/CodeGen/AArch64/aarch64-smull.ll @@ -2265,33 +2265,12 @@ define <2 x i64> @lsr_const(<2 x i64> %a, <2 x i64> %b) { } define <2 x i64> @asr(<2 x i64> %a, <2 x i64> %b) { -; CHECK-NEON-LABEL: asr: -; CHECK-NEON: // %bb.0: -; CHECK-NEON-NEXT: shrn v0.2s, v0.2d, #32 -; CHECK-NEON-NEXT: shrn v1.2s, v1.2d, #32 -; CHECK-NEON-NEXT: smull v0.2d, v0.2s, v1.2s -; CHECK-NEON-NEXT: ret -; -; CHECK-SVE-LABEL: asr: -; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: shrn v0.2s, v0.2d, #32 -; CHECK-SVE-NEXT: shrn v1.2s, v1.2d, #32 -; CHECK-SVE-NEXT: smull v0.2d, v0.2s, v1.2s -; CHECK-SVE-NEXT: ret -; -; CHECK-GI-LABEL: asr: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: sshr v0.2d, v0.2d, #32 -; CHECK-GI-NEXT: sshr v1.2d, v1.2d, #32 -; CHECK-GI-NEXT: fmov x8, d0 -; CHECK-GI-NEXT: fmov x9, d1 -; CHECK-GI-NEXT: mov x10, v0.d[1] -; CHECK-GI-NEXT: mov x11, v1.d[1] -; CHECK-GI-NEXT: mul x8, x8, x9 -; CHECK-GI-NEXT: mul x9, x10, x11 -; CHECK-GI-NEXT: mov v0.d[0], x8 -; CHECK-GI-NEXT: mov v0.d[1], x9 -; CHECK-GI-NEXT: ret +; CHECK-LABEL: asr: +; CHECK: // %bb.0: +; CHECK-NEXT: shrn v0.2s, v0.2d, #32 +; CHECK-NEXT: shrn v1.2s, v1.2d, #32 +; CHECK-NEXT: smull v0.2d, v0.2s, v1.2s +; CHECK-NEXT: ret %x = ashr <2 x i64> %a, <i64 32, i64 32> %y = ashr <2 x i64> %b, <i64 32, i64 32> %z = mul nsw <2 x i64> %x, %y @@ -2299,34 +2278,12 @@ define <2 x i64> @asr(<2 x i64> %a, <2 x i64> %b) { } define <2 x i64> @asr_const(<2 x i64> %a, <2 x i64> %b) { -; CHECK-NEON-LABEL: asr_const: -; CHECK-NEON: // %bb.0: -; CHECK-NEON-NEXT: movi v1.2s, #31 -; CHECK-NEON-NEXT: shrn v0.2s, v0.2d, #32 -; CHECK-NEON-NEXT: smull v0.2d, v0.2s, v1.2s -; CHECK-NEON-NEXT: ret -; -; CHECK-SVE-LABEL: asr_const: -; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: movi v1.2s, #31 -; CHECK-SVE-NEXT: shrn v0.2s, v0.2d, #32 -; CHECK-SVE-NEXT: smull v0.2d, v0.2s, v1.2s -; CHECK-SVE-NEXT: ret -; -; CHECK-GI-LABEL: asr_const: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: adrp x8, .LCPI81_0 -; CHECK-GI-NEXT: sshr v0.2d, v0.2d, #32 -; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI81_0] -; CHECK-GI-NEXT: fmov x8, d0 -; CHECK-GI-NEXT: fmov x9, d1 -; CHECK-GI-NEXT: mov x10, v0.d[1] -; CHECK-GI-NEXT: mov x11, v1.d[1] -; CHECK-GI-NEXT: mul x8, x8, x9 -; CHECK-GI-NEXT: mul x9, x10, x11 -; CHECK-GI-NEXT: mov v0.d[0], x8 -; CHECK-GI-NEXT: mov v0.d[1], x9 -; CHECK-GI-NEXT: ret +; CHECK-LABEL: asr_const: +; CHECK: // %bb.0: +; CHECK-NEXT: movi v1.2s, #31 +; CHECK-NEXT: shrn v0.2s, v0.2d, #32 +; CHECK-NEXT: smull v0.2d, v0.2s, v1.2s +; CHECK-NEXT: ret %x = ashr <2 x i64> %a, <i64 32, i64 32> %z = mul nsw <2 x i64> %x, <i64 31, i64 31> ret <2 x i64> %z diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir index 78a2227b84a3a..a7c1c6355bff6 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir @@ -88,8 +88,7 @@ body: | ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASSERT_SEXT]], [[ASHR]] ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[SEXT_INREG]], [[ASHR]] - ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[XOR]], 32 - ; RV64I-NEXT: $x10 = COPY [[SEXT_INREG1]](s64) + ; RV64I-NEXT: $x10 = COPY [[XOR]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; ; RV64ZBB-LABEL: name: abs_i32 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll index 8549a7c526e45..747dda692529e 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll @@ -1053,9 +1053,8 @@ define signext i32 @abs_i32_sext(i32 signext %x) { ; RV64I-LABEL: abs_i32_sext: ; RV64I: # %bb.0: ; RV64I-NEXT: srai a1, a0, 31 -; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: addw a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1 -; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: ret ; ; RV64ZBB-LABEL: abs_i32_sext: `````````` </details> https://github.com/llvm/llvm-project/pull/139503 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
