https://github.com/davemgreen created
https://github.com/llvm/llvm-project/pull/139505
The code is similar to computeKnownBits and the code in
SelectionDAG::ComputeNumSignBits.
>From 68fc0c493331eaa56ebc862ef7dfb7106cabad82 Mon Sep 17 00:00:00 2001
From: David Green <david.gr...@arm.com>
Date: Mon, 12 May 2025 07:36:16 +0100
Subject: [PATCH] [GlobalISel] Add computeKnownBits for G_SHUFFLE_VECTOR
The code is similar to computeKnownBits and the code in
SelectionDAG::ComputeNumSignBits
---
.../CodeGen/GlobalISel/GISelValueTracking.cpp | 24 +++++++++++
llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll | 33 +++++----------
.../AArch64/aarch64-matrix-umull-smull.ll | 41 +++++++------------
3 files changed, 49 insertions(+), 49 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index 41e36e1e6640b..fb483ed962270 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -874,6 +874,30 @@ unsigned GISelValueTracking::computeNumSignBits(Register R,
SrcTy.getScalarSizeInBits());
break;
}
+ case TargetOpcode::G_SHUFFLE_VECTOR: {
+ // Collect the minimum number of sign bits that are shared by every vector
+ // element referenced by the shuffle.
+ APInt DemandedLHS, DemandedRHS;
+ unsigned NumElts = MRI.getType(MI.getOperand(1).getReg()).getNumElements();
+ if (!getShuffleDemandedElts(NumElts, MI.getOperand(3).getShuffleMask(),
+ DemandedElts, DemandedLHS, DemandedRHS))
+ return 1;
+
+ unsigned Tmp = std::numeric_limits<unsigned>::max();
+ if (!!DemandedLHS)
+ Tmp =
+ computeNumSignBits(MI.getOperand(1).getReg(), DemandedLHS, Depth +
1);
+ if (!!DemandedRHS) {
+ unsigned Tmp2 =
+ computeNumSignBits(MI.getOperand(2).getReg(), DemandedRHS, Depth +
1);
+ Tmp = std::min(Tmp, Tmp2);
+ }
+ // If we don't know anything, early out and try computeKnownBits fall-back.
+ if (Tmp == 1)
+ break;
+ assert(Tmp <= TyBits && "Failed to determine minimum sign bits");
+ return Tmp;
+ }
case TargetOpcode::G_INTRINSIC:
case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
case TargetOpcode::G_INTRINSIC_CONVERGENT:
diff --git a/llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
b/llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
index 56393142726c7..d86cbf57a65f3 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
@@ -400,9 +400,10 @@ define <8 x i16> @missing_insert(<8 x i8> %b) {
;
; CHECK-GI-LABEL: missing_insert:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
-; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #4
-; CHECK-GI-NEXT: mul v0.8h, v1.8h, v0.8h
+; CHECK-GI-NEXT: sshll v1.8h, v0.8b, #0
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #4
+; CHECK-GI-NEXT: xtn v1.8b, v1.8h
+; CHECK-GI-NEXT: smull v0.8h, v1.8b, v0.8b
; CHECK-GI-NEXT: ret
entry:
%ext.b = sext <8 x i8> %b to <8 x i16>
@@ -421,10 +422,10 @@ define <8 x i16> @shufsext_v8i8_v8i16(<8 x i8> %src, <8 x
i8> %b) {
; CHECK-GI-LABEL: shufsext_v8i8_v8i16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
-; CHECK-GI-NEXT: sshll v1.8h, v1.8b, #0
; CHECK-GI-NEXT: rev64 v0.8h, v0.8h
; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-GI-NEXT: mul v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: smull v0.8h, v0.8b, v1.8b
; CHECK-GI-NEXT: ret
entry:
%in = sext <8 x i8> %src to <8 x i16>
@@ -444,16 +445,9 @@ define <2 x i64> @shufsext_v2i32_v2i64(<2 x i32> %src, <2
x i32> %b) {
; CHECK-GI-LABEL: shufsext_v2i32_v2i64:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: sshll v0.2d, v0.2s, #0
-; CHECK-GI-NEXT: sshll v1.2d, v1.2s, #0
; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-GI-NEXT: fmov x9, d1
-; CHECK-GI-NEXT: mov x11, v1.d[1]
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov x10, v0.d[1]
-; CHECK-GI-NEXT: mul x8, x8, x9
-; CHECK-GI-NEXT: mul x9, x10, x11
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: smull v0.2d, v0.2s, v1.2s
; CHECK-GI-NEXT: ret
entry:
%in = sext <2 x i32> %src to <2 x i64>
@@ -496,16 +490,9 @@ define <2 x i64> @shufzext_v2i32_v2i64(<2 x i32> %src, <2
x i32> %b) {
; CHECK-GI-LABEL: shufzext_v2i32_v2i64:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: sshll v0.2d, v0.2s, #0
-; CHECK-GI-NEXT: sshll v1.2d, v1.2s, #0
; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-GI-NEXT: fmov x9, d1
-; CHECK-GI-NEXT: mov x11, v1.d[1]
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov x10, v0.d[1]
-; CHECK-GI-NEXT: mul x8, x8, x9
-; CHECK-GI-NEXT: mul x9, x10, x11
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: smull v0.2d, v0.2s, v1.2s
; CHECK-GI-NEXT: ret
entry:
%in = sext <2 x i32> %src to <2 x i64>
diff --git a/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
b/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
index eee1ec0b37315..b89b422c8c5ad 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
@@ -834,30 +834,18 @@ define void @sink_v4i64_1(ptr %p, ptr %d, i64 %n, <2 x
i32> %a) {
; CHECK-GI-NEXT: sshll v0.2d, v0.2s, #0
; CHECK-GI-NEXT: mov x8, xzr
; CHECK-GI-NEXT: dup v0.2d, v0.d[1]
-; CHECK-GI-NEXT: mov x9, v0.d[1]
-; CHECK-GI-NEXT: fmov x10, d0
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
; CHECK-GI-NEXT: .LBB7_1: // %loop
; CHECK-GI-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-GI-NEXT: ldr q0, [x0]
+; CHECK-GI-NEXT: ldr q1, [x0]
; CHECK-GI-NEXT: subs x2, x2, #8
; CHECK-GI-NEXT: add x8, x8, #8
-; CHECK-GI-NEXT: sshll v1.2d, v0.2s, #0
-; CHECK-GI-NEXT: sshll2 v0.2d, v0.4s, #0
-; CHECK-GI-NEXT: fmov x11, d1
-; CHECK-GI-NEXT: mov x12, v1.d[1]
-; CHECK-GI-NEXT: fmov x13, d0
-; CHECK-GI-NEXT: mov x14, v0.d[1]
-; CHECK-GI-NEXT: mul x11, x11, x10
-; CHECK-GI-NEXT: mul x13, x13, x10
-; CHECK-GI-NEXT: mul x12, x12, x9
-; CHECK-GI-NEXT: mov v0.d[0], x11
-; CHECK-GI-NEXT: mul x11, x14, x9
-; CHECK-GI-NEXT: mov v1.d[0], x13
-; CHECK-GI-NEXT: mov v0.d[1], x12
-; CHECK-GI-NEXT: mov v1.d[1], x11
-; CHECK-GI-NEXT: shrn v0.2s, v0.2d, #15
-; CHECK-GI-NEXT: shrn2 v0.4s, v1.2d, #15
-; CHECK-GI-NEXT: str q0, [x0], #32
+; CHECK-GI-NEXT: mov d2, v1.d[1]
+; CHECK-GI-NEXT: smull v1.2d, v1.2s, v0.2s
+; CHECK-GI-NEXT: smull v2.2d, v2.2s, v0.2s
+; CHECK-GI-NEXT: shrn v1.2s, v1.2d, #15
+; CHECK-GI-NEXT: shrn2 v1.4s, v2.2d, #15
+; CHECK-GI-NEXT: str q1, [x0], #32
; CHECK-GI-NEXT: b.ne .LBB7_1
; CHECK-GI-NEXT: // %bb.2: // %exit
; CHECK-GI-NEXT: ret
@@ -971,18 +959,19 @@ define void @sink_v16s16_8(ptr %p, ptr %d, i64 %n, <16 x
i8> %a) {
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: sshll2 v0.8h, v0.16b, #0
; CHECK-GI-NEXT: mov x8, xzr
+; CHECK-GI-NEXT: dup v0.8h, v0.h[2]
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
; CHECK-GI-NEXT: .LBB9_1: // %loop
; CHECK-GI-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-GI-NEXT: ldr q1, [x0]
; CHECK-GI-NEXT: subs x2, x2, #8
; CHECK-GI-NEXT: add x8, x8, #8
-; CHECK-GI-NEXT: sshll v2.8h, v1.8b, #0
-; CHECK-GI-NEXT: sshll2 v1.8h, v1.16b, #0
-; CHECK-GI-NEXT: mul v2.8h, v2.8h, v0.h[2]
-; CHECK-GI-NEXT: mul v1.8h, v1.8h, v0.h[2]
-; CHECK-GI-NEXT: sshr v2.8h, v2.8h, #15
+; CHECK-GI-NEXT: mov d2, v1.d[1]
+; CHECK-GI-NEXT: smull v1.8h, v1.8b, v0.8b
+; CHECK-GI-NEXT: smull v2.8h, v2.8b, v0.8b
; CHECK-GI-NEXT: sshr v1.8h, v1.8h, #15
-; CHECK-GI-NEXT: uzp1 v1.16b, v2.16b, v1.16b
+; CHECK-GI-NEXT: sshr v2.8h, v2.8h, #15
+; CHECK-GI-NEXT: uzp1 v1.16b, v1.16b, v2.16b
; CHECK-GI-NEXT: str q1, [x0], #32
; CHECK-GI-NEXT: b.ne .LBB9_1
; CHECK-GI-NEXT: // %bb.2: // %exit
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