================ @@ -1583,6 +1583,26 @@ bool IRTranslator::translateCast(unsigned Opcode, const User &U, return true; } +bool IRTranslator::translatePtrToAddr(const User &U, + MachineIRBuilder &MIRBuilder) { + if (containsBF16Type(U)) + return false; + + uint32_t Flags = 0; + if (const Instruction *I = dyn_cast<Instruction>(&U)) + Flags = MachineInstr::copyFlagsFromInstruction(*I); + + Register Op = getOrCreateVReg(*U.getOperand(0)); + Type *PtrTy = U.getOperand(0)->getType(); + LLT AddrTy = getLLTForType(*DL->getIndexType(PtrTy), *DL); + auto IntPtrTy = getLLTForType(*DL->getIntPtrType(PtrTy), *DL); + auto PtrToInt = MIRBuilder.buildPtrToInt(IntPtrTy, Op); ---------------- arsenm wrote:
In general I expect a 1:1 mapping with IR opcodes https://github.com/llvm/llvm-project/pull/139601 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits