[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)

[Craig Topper via llvm-branch-commits]

================
@@ -25,95 +25,119 @@ defvar QExtsRV64 = [QExt];
 
//===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtQ] in {
-  let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
-  def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd),
-              (ins GPRMem:$rs1, simm12:$imm12),
-              "flq", "$rd, ${imm12}(${rs1})">;
+  def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
+
   // Operands for stores are in the order srcreg, base, offset rather than
   // reflecting the order these fields are specified in the instruction
   // encoding.
-  let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
-  def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs),
-              (ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12),
-              "fsq", "$rs2, ${imm12}(${rs1})">;
+  def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
 } // Predicates = [HasStdExtQ]
 
 foreach Ext = QExts in {
-  defm FMADD_Q : FPFMA_rrr_frm_m<OPC_MADD, 0b11, "fmadd.q", Ext>;
-  defm FMSUB_Q : FPFMA_rrr_frm_m<OPC_MSUB, 0b11, "fmsub.q", Ext>;
-  defm FNMSUB_Q : FPFMA_rrr_frm_m<OPC_NMSUB, 0b11, "fnmsub.q", Ext>;
-  defm FNMADD_Q : FPFMA_rrr_frm_m<OPC_NMADD, 0b11, "fnmadd.q", Ext>;
+  let SchedRW = [WriteFMA128, ReadFMA128, ReadFMA128, ReadFMA128Addend] in {
+    defm FMADD_Q : FPFMA_rrr_frm_m<OPC_MADD, 0b11, "fmadd.q", Ext>;
+    defm FMSUB_Q : FPFMA_rrr_frm_m<OPC_MSUB, 0b11, "fmsub.q", Ext>;
+    defm FNMSUB_Q : FPFMA_rrr_frm_m<OPC_NMSUB, 0b11, "fnmsub.q", Ext>;
+    defm FNMADD_Q : FPFMA_rrr_frm_m<OPC_NMADD, 0b11, "fnmadd.q", Ext>;
+  }
 
-  defm FADD_Q : FPALU_rr_frm_m<0b0000011, "fadd.q", Ext>;
-  defm FSUB_Q : FPALU_rr_frm_m<0b0000111, "fsub.q", Ext>;
+  let SchedRW = [WriteFAdd128, ReadFAdd128, ReadFAdd128] in {
+    defm FADD_Q : FPALU_rr_frm_m<0b0000011, "fadd.q", Ext>;
+    defm FSUB_Q : FPALU_rr_frm_m<0b0000111, "fsub.q", Ext>;
+  }
 
+  let SchedRW = [WriteFMul128, ReadFMul128, ReadFMul128] in 
----------------
topperc wrote:

Please don't suggest things that diverge from RISCVInstrInfoF.td, 
RISCVInstrInfoD.td, and RISCVInstrInfoZfh.td.

https://github.com/llvm/llvm-project/pull/139495
_______________________________________________
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits