================
@@ -102,6 +102,49 @@ class F2_4<bit annul, bit pred, dag outs, dag ins,
   let Inst{13-0}  = imm16{13-0};
 }
 
+class F2_5<bit cc, dag outs, dag ins, string asmstr,
+           list<dag> pattern = [], InstrItinClass itin = NoItinerary>
+   : InstSP<outs, ins, asmstr, pattern, itin> {
----------------
s-barannikov wrote:

```suggestion
    : InstSP<outs, ins, asmstr, pattern, itin> {
```

https://github.com/llvm/llvm-project/pull/138403
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