https://github.com/nikic created https://github.com/llvm/llvm-project/pull/143163
Backport of https://github.com/llvm/llvm-project/commit/32837f376f3c795d3ae6e632adc4f1a60180a646. >From 2c1c9730974c384b10bccc9f4a4f63c94377d302 Mon Sep 17 00:00:00 2001 From: David Green <david.gr...@arm.com> Date: Thu, 29 May 2025 10:22:24 +0100 Subject: [PATCH] release/20.x: [AArch64] Handle XAR with v1i64 operand types (#141754) When converting ROTR(XOR(a, b)) to XAR(a, b), or ROTR(a, a) to XAR(a, zero) we were not handling v1i64 types, meaning illegal copies get generated. This addresses that by generating insert_subreg and extract_subreg for v1i64 to keep the values with the correct types. Fixes #141746 --- .../Target/AArch64/AArch64ISelDAGToDAG.cpp | 24 ++++++++++++++++++- llvm/test/CodeGen/AArch64/xar.ll | 20 ++++++++++++++++ 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index 1387a224fa660..0aad7665f6216 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -4608,9 +4608,31 @@ bool AArch64DAGToDAGISel::trySelectXAR(SDNode *N) { if (ShAmt + HsAmt != 64) return false; + // If the input is a v1i64, widen to a v2i64 to use XAR. + assert((VT == MVT::v1i64 || VT == MVT::v2i64) && "Unexpected XAR type!"); + if (VT == MVT::v1i64) { + EVT SVT = MVT::v2i64; + SDValue Undef = + SDValue(CurDAG->getMachineNode(AArch64::IMPLICIT_DEF, DL, SVT), 0); + SDValue DSub = CurDAG->getTargetConstant(AArch64::dsub, DL, MVT::i32); + R1 = SDValue(CurDAG->getMachineNode(AArch64::INSERT_SUBREG, DL, SVT, Undef, + R1, DSub), + 0); + if (R2.getValueType() == MVT::v1i64) + R2 = SDValue(CurDAG->getMachineNode(AArch64::INSERT_SUBREG, DL, SVT, + Undef, R2, DSub), + 0); + } + SDValue Ops[] = {R1, R2, Imm}; - CurDAG->SelectNodeTo(N, AArch64::XAR, N0.getValueType(), Ops); + SDNode *XAR = CurDAG->getMachineNode(AArch64::XAR, DL, MVT::v2i64, Ops); + if (VT == MVT::v1i64) { + SDValue DSub = CurDAG->getTargetConstant(AArch64::dsub, DL, MVT::i32); + XAR = CurDAG->getMachineNode(AArch64::EXTRACT_SUBREG, DL, VT, + SDValue(XAR, 0), DSub); + } + ReplaceNode(N, XAR); return true; } diff --git a/llvm/test/CodeGen/AArch64/xar.ll b/llvm/test/CodeGen/AArch64/xar.ll index d050eaf6646de..5666ab35cde48 100644 --- a/llvm/test/CodeGen/AArch64/xar.ll +++ b/llvm/test/CodeGen/AArch64/xar.ll @@ -19,4 +19,24 @@ define <2 x i64> @xar(<2 x i64> %x, <2 x i64> %y) { ret <2 x i64> %b } +define <1 x i64> @xar_v1i64(<1 x i64> %a, <1 x i64> %b) { +; SHA3-LABEL: xar_v1i64: +; SHA3: // %bb.0: +; SHA3-NEXT: // kill: def $d0 killed $d0 def $q0 +; SHA3-NEXT: // kill: def $d1 killed $d1 def $q1 +; SHA3-NEXT: xar v0.2d, v0.2d, v1.2d, #63 +; SHA3-NEXT: // kill: def $d0 killed $d0 killed $q0 +; SHA3-NEXT: ret +; +; NOSHA3-LABEL: xar_v1i64: +; NOSHA3: // %bb.0: +; NOSHA3-NEXT: eor v1.8b, v0.8b, v1.8b +; NOSHA3-NEXT: shl d0, d1, #1 +; NOSHA3-NEXT: usra d0, d1, #63 +; NOSHA3-NEXT: ret + %v.val = xor <1 x i64> %a, %b + %fshl = tail call <1 x i64> @llvm.fshl.v1i64(<1 x i64> %v.val, <1 x i64> %v.val, <1 x i64> splat (i64 1)) + ret <1 x i64> %fshl +} + declare <2 x i64> @llvm.fshl.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
