https://github.com/rampitec created https://github.com/llvm/llvm-project/pull/143430
None >From 1d58dc465ebd0049e9f4d6b9c32b65b72b88be3e Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin <stanislav.mekhanos...@amd.com> Date: Mon, 9 Jun 2025 12:47:55 -0700 Subject: [PATCH] [AMDGPU] Autogenerate bitop3 asm and dags. NFCI. --- llvm/lib/Target/AMDGPU/SIInstrInfo.td | 38 +++++++++++++--------- llvm/lib/Target/AMDGPU/VOP3Instructions.td | 13 +------- 2 files changed, 24 insertions(+), 27 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index a78440dc7a1f4..2c20475726a48 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -1973,7 +1973,8 @@ class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC, RegisterOperand Src2RC, int NumSrcArgs, bit HasClamp, bit HasModifiers, bit HasSrc2Mods, bit HasOMod, Operand Src0Mod, Operand Src1Mod, Operand Src2Mod, - bit HasFP8ByteSel = 0, bit HasFP8DstByteSel = 0> { + bit HasFP8ByteSel = 0, bit HasFP8DstByteSel = 0, + bit HasBitOp3 = 0> { dag src0 = !if(!ge(NumSrcArgs, 1), !if (HasModifiers, (ins Src0Mod:$src0_modifiers, Src0RC:$src0), @@ -1999,21 +2000,23 @@ class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC, !con(!if(HasFP8DstByteSel, (ins VGPR_32:$vdst_in), (ins)), (ins ByteSel0:$byte_sel)), (ins)); + dag bitop3 = !if(HasBitOp3, (ins bitop3_0:$bitop3), (ins)); - dag ret = !con(src0, src1, src2, clamp, omod, bytesel); + dag ret = !con(src0, src1, src2, clamp, omod, bytesel, bitop3); } class getInsVOP3Base<RegisterOperand Src0RC, RegisterOperand Src1RC, RegisterOperand Src2RC, int NumSrcArgs, bit HasClamp, bit HasModifiers, bit HasSrc2Mods, bit HasOMod, Operand Src0Mod, Operand Src1Mod, Operand Src2Mod, bit HasOpSel, - bit HasFP8ByteSel = 0, bit HasFP8DstByteSel = 0> { + bit HasFP8ByteSel = 0, bit HasFP8DstByteSel = 0, bit HasBitOp3 = 0> { // getInst64 handles clamp and omod. implicit mutex between vop3p and omod dag base = getIns64 <Src0RC, Src1RC, Src2RC, NumSrcArgs, HasClamp, HasModifiers, HasSrc2Mods, HasOMod, Src0Mod, Src1Mod, Src2Mod, HasFP8ByteSel, HasFP8DstByteSel>.ret; dag opsel = (ins op_sel0:$op_sel); - dag ret = !con(base, !if(HasOpSel, opsel, (ins))); + dag bitop3 = (ins bitop3_0:$bitop3); + dag ret = !con(base, !if(HasBitOp3, bitop3, (ins)), !if(HasOpSel, opsel, (ins))); } class getInsVOP3P <RegisterOperand Src0RC, RegisterOperand Src1RC, @@ -2035,12 +2038,12 @@ class getInsVOP3OpSel <RegisterOperand Src0RC, RegisterOperand Src1RC, RegisterOperand Src2RC, int NumSrcArgs, bit HasClamp, bit HasOMod, Operand Src0Mod, Operand Src1Mod, Operand Src2Mod, - bit HasFP8ByteSel = 0, bit HasFP8DstByteSel = 0> { + bit HasFP8ByteSel = 0, bit HasFP8DstByteSel = 0, bit HasBitOp3 = 0> { dag ret = getInsVOP3Base<Src0RC, Src1RC, Src2RC, NumSrcArgs, HasClamp, 1/*HasModifiers*/, 1/*HasSrc2Mods*/, HasOMod, Src0Mod, Src1Mod, Src2Mod, /*HasOpSel=*/1, - HasFP8ByteSel, HasFP8DstByteSel>.ret; + HasFP8ByteSel, HasFP8DstByteSel, HasBitOp3>.ret; } class getInsDPPBase <RegisterOperand OldRC, RegisterOperand Src0RC, RegisterOperand Src1RC, @@ -2247,7 +2250,8 @@ class getAsmVOP3OpSel <int NumSrcArgs, bit Src0HasMods, bit Src1HasMods, bit Src2HasMods, - bit HasByteSel = 0> { + bit HasByteSel = 0, + bit HasBitOp3 = 0> { string dst = "$vdst"; string isrc0 = !if(!eq(NumSrcArgs, 1), "$src0", "$src0,"); @@ -2269,7 +2273,8 @@ class getAsmVOP3OpSel <int NumSrcArgs, string bytesel = !if(HasByteSel, "$byte_sel", ""); string clamp = !if(HasClamp, "$clamp", ""); string omod = !if(HasOMod, "$omod", ""); - string ret = dst#", "#src0#src1#src2#"$op_sel"#bytesel#clamp#omod; + string bitop3 = !if(HasBitOp3, "$bitop3", ""); + string ret = dst#", "#src0#src1#src2#bitop3#"$op_sel"#bytesel#clamp#omod; } class getAsmDPP <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32> { @@ -2301,7 +2306,7 @@ class getAsmVOP3Base <int NumSrcArgs, bit HasDst, bit HasClamp, bit HasOpSel, bit HasOMod, bit IsVOP3P, bit HasNeg, bit Src0HasMods, bit Src1HasMods, bit Src2HasMods, ValueType DstVT = i32, - bit HasByteSel = 0> { + bit HasByteSel = 0, bit HasBitOp3 = 0> { string dst = !if(HasDst, !if(!eq(DstVT.Size, 1), "$sdst", @@ -2324,6 +2329,7 @@ class getAsmVOP3Base <int NumSrcArgs, bit HasDst, bit HasClamp, string src2 = !if(Src2HasMods, src2mods, src2nomods); string opsel = !if(HasOpSel, "$op_sel", ""); string bytesel = !if(HasByteSel, "$byte_sel", ""); + string bitop3 = !if(HasBitOp3, "$bitop3", ""); string 3PMods = !if(IsVOP3P, !if(HasOpSel, "$op_sel_hi", "") #!if(HasNeg, "$neg_lo$neg_hi", ""), @@ -2333,7 +2339,7 @@ class getAsmVOP3Base <int NumSrcArgs, bit HasDst, bit HasClamp, string ret = dst#!if(!eq(NumSrcArgs,0), "", - !if(HasDst,", ", "")#src0#src1#src2#opsel#bytesel#3PMods#clamp#omod); + !if(HasDst,", ", "")#src0#src1#src2#bitop3#opsel#bytesel#3PMods#clamp#omod); } class getAsmVOP3DPP<string base> { @@ -2558,6 +2564,7 @@ class VOPProfile <list<ValueType> _ArgVT, bit _EnableClamp = 0> { field bit HasFP8DstByteSel = 0; field bit HasFP4DstByteSel = 0; field bit HasFP8ByteSel = !or(HasFP8SrcByteSel, HasFP8DstByteSel); + field bit HasBitOp3 = 0; field bit HasDst = !ne(DstVT.Value, untyped.Value); field bit HasDst32 = HasDst; @@ -2628,14 +2635,14 @@ class VOPProfile <list<ValueType> _ArgVT, bit _EnableClamp = 0> { field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs, HasClamp, HasModifiers, HasSrc2Mods, HasOMod, Src0Mod, Src1Mod, Src2Mod, - HasFP8ByteSel, HasFP8DstByteSel>.ret; + HasFP8ByteSel, HasFP8DstByteSel, HasBitOp3>.ret; field dag InsVOP3P = getInsVOP3P<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs, HasClamp, HasOpSel, HasNeg, Src0PackedMod, Src1PackedMod, Src2PackedMod>.ret; field dag InsVOP3OpSel = getInsVOP3OpSel<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs, HasClamp, HasOMod, Src0Mod, Src1Mod, Src2Mod, - HasFP8ByteSel, HasFP8DstByteSel>.ret; + HasFP8ByteSel, HasFP8DstByteSel, HasBitOp3>.ret; field dag InsDPP = !if(HasExtDPP, getInsDPP<DstRCDPP, Src0DPP, Src1DPP, Src2DPP, NumSrcArgs, HasModifiers, Src0ModDPP, Src1ModDPP, Src2ModDPP>.ret, @@ -2648,7 +2655,7 @@ class VOPProfile <list<ValueType> _ArgVT, bit _EnableClamp = 0> { defvar InsVOP3DPPBase = getInsVOP3Base<Src0VOP3DPP, Src1VOP3DPP, Src2VOP3DPP, NumSrcArgs, HasClamp, HasModifiers, HasSrc2Mods, HasOMod, Src0ModVOP3DPP, Src1ModVOP3DPP, Src2ModVOP3DPP, HasOpSel, - HasFP8ByteSel, HasFP8DstByteSel>.ret; + HasFP8ByteSel, HasFP8DstByteSel, HasBitOp3>.ret; defvar InsVOP3PDPPBase = getInsVOP3P<Src0VOP3DPP, Src1VOP3DPP, Src2VOP3DPP, NumSrcArgs, HasClamp, HasOpSel, HasNeg, Src0ModVOP3DPP, Src1ModVOP3DPP, Src2ModVOP3DPP>.ret; @@ -2677,7 +2684,7 @@ class VOPProfile <list<ValueType> _ArgVT, bit _EnableClamp = 0> { field string AsmDPP8 = getAsmDPP8<HasDst, NumSrcArgs, 0 /*HasModifiers*/, DstVT>.ret; field string AsmVOP3Base = getAsmVOP3Base<NumSrcArgs, HasDst, HasClamp, HasOpSel, HasOMod, IsVOP3P, HasNeg, HasSrc0Mods, HasSrc1Mods, - HasSrc2Mods, DstVT, HasFP8ByteSel>.ret; + HasSrc2Mods, DstVT, HasFP8ByteSel, HasBitOp3>.ret; field string Asm64 = AsmVOP3Base; field string AsmVOP3P = getAsmVOP3P<HasDst, NumSrcArgs, HasNeg, HasClamp, HasOpSel>.ret; field string AsmVOP3OpSel = getAsmVOP3OpSel<NumSrcArgs, @@ -2686,7 +2693,8 @@ class VOPProfile <list<ValueType> _ArgVT, bit _EnableClamp = 0> { HasSrc0FloatMods, HasSrc1FloatMods, HasSrc2FloatMods, - HasFP8ByteSel>.ret; + HasFP8ByteSel, + HasBitOp3>.ret; field string AsmVOP3DPP = getAsmVOP3DPP<AsmVOP3Base>.ret; field string AsmVOP3DPP16 = getAsmVOP3DPP16<AsmVOP3Base>.ret; field string AsmVOP3DPP8 = getAsmVOP3DPP8<AsmVOP3Base>.ret; diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td index 046cce73ff761..ef88a379f3680 100644 --- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td @@ -1003,18 +1003,7 @@ class VOP3_BITOP3_Profile<VOPProfile pfl, VOP3Features f> : VOP3_Profile<pfl, f> let HasClamp = 0; let HasOMod = 0; let HasModifiers = 0; - - let Ins64 = !con(getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs, - 0 /* HasIntClamp */, HasModifiers, HasSrc2Mods, - HasOMod, Src0Mod, Src1Mod, Src2Mod>.ret, - (ins bitop3_0:$bitop3)); - - let InsVOP3OpSel = !con(getInsVOP3Base<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs, 0, 1, 1, 0, - Src0Mod, Src1Mod, Src2Mod, 0>.ret, - (ins bitop3_0:$bitop3, op_sel0:$op_sel)); - - let Asm64 = "$vdst, $src0, $src1, $src2$bitop3"; - let AsmVOP3OpSel = !subst("$op_sel", "$bitop3$op_sel", getAsmVOP3OpSel<3, 0, 0, 0, 0, 0>.ret); + let HasBitOp3 = 1; } class VOP3_CVT_SCALE_F1632_FP8BF8_Profile<ValueType DstTy> : VOP3_Profile<VOPProfile<[DstTy, i32, f32, untyped]>, _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits