https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/142778
>From ecde1e11361f5400e820cb117d6c62100906f5b6 Mon Sep 17 00:00:00 2001
From: Fabian Ritter <fabian.rit...@amd.com>
Date: Wed, 4 Jun 2025 09:48:02 -0400
Subject: [PATCH] [AMDGPU][SDAG] Handle ISD::PTRADD in
SelectionDAGAddressAnalysis
This is used in a bunch of memory-related transforms.
For SWDEV-516125.
---
.../SelectionDAGAddressAnalysis.cpp | 6 ++--
.../AMDGPU/ptradd-sdag-optimizations.ll | 28 ++++++-------------
2 files changed, 11 insertions(+), 23 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp
b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp
index f2ab88851b780..da92aaa860b2b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp
@@ -231,6 +231,7 @@ static BaseIndexOffset matchLSNode(const LSBaseSDNode *N,
}
break;
case ISD::ADD:
+ case ISD::PTRADD:
if (auto *C = dyn_cast<ConstantSDNode>(Base->getOperand(1))) {
Offset += C->getSExtValue();
Base = DAG.getTargetLoweringInfo().unwrapAddress(Base->getOperand(0));
@@ -259,7 +260,7 @@ static BaseIndexOffset matchLSNode(const LSBaseSDNode *N,
break;
}
- if (Base->getOpcode() == ISD::ADD) {
+ if (Base->isAnyAdd()) {
// TODO: The following code appears to be needless as it just
// bails on some Ptrs early, reducing the cases where we
// find equivalence. We should be able to remove this.
@@ -282,8 +283,7 @@ static BaseIndexOffset matchLSNode(const LSBaseSDNode *N,
}
// Check if Index Offset pattern
- if (Index->getOpcode() != ISD::ADD ||
- !isa<ConstantSDNode>(Index->getOperand(1)))
+ if (!Index->isAnyAdd() || !isa<ConstantSDNode>(Index->getOperand(1)))
return BaseIndexOffset(PotentialBase, Index, Offset, IsIndexSignExt);
Offset += cast<ConstantSDNode>(Index->getOperand(1))->getSExtValue();
diff --git a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
index d3242905ada64..2e76033a480f4 100644
--- a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
+++ b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
@@ -130,26 +130,14 @@ define amdgpu_kernel void @llvm_amdgcn_queue_ptr(ptr
addrspace(1) %ptr) #0 {
; Taken from memcpy-param-combinations.ll, tests PTRADD handling in
; SelectionDAGAddressAnalysis.
define void @memcpy_p1_p4_sz16_align_1_1(ptr addrspace(1) align 1 %dst, ptr
addrspace(4) align 1 readonly %src) {
-; GFX942_PTRADD-LABEL: memcpy_p1_p4_sz16_align_1_1:
-; GFX942_PTRADD: ; %bb.0: ; %entry
-; GFX942_PTRADD-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942_PTRADD-NEXT: global_load_dwordx2 v[4:5], v[2:3], off
-; GFX942_PTRADD-NEXT: s_waitcnt vmcnt(0)
-; GFX942_PTRADD-NEXT: global_store_dwordx2 v[0:1], v[4:5], off
-; GFX942_PTRADD-NEXT: global_load_dwordx2 v[2:3], v[2:3], off offset:8
-; GFX942_PTRADD-NEXT: s_waitcnt vmcnt(0)
-; GFX942_PTRADD-NEXT: global_store_dwordx2 v[0:1], v[2:3], off offset:8
-; GFX942_PTRADD-NEXT: s_waitcnt vmcnt(0)
-; GFX942_PTRADD-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX942_LEGACY-LABEL: memcpy_p1_p4_sz16_align_1_1:
-; GFX942_LEGACY: ; %bb.0: ; %entry
-; GFX942_LEGACY-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942_LEGACY-NEXT: global_load_dwordx4 v[2:5], v[2:3], off
-; GFX942_LEGACY-NEXT: s_waitcnt vmcnt(0)
-; GFX942_LEGACY-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
-; GFX942_LEGACY-NEXT: s_waitcnt vmcnt(0)
-; GFX942_LEGACY-NEXT: s_setpc_b64 s[30:31]
+; GFX942-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942: ; %bb.0: ; %entry
+; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: global_load_dwordx4 v[2:5], v[2:3], off
+; GFX942-NEXT: s_waitcnt vmcnt(0)
+; GFX942-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
+; GFX942-NEXT: s_waitcnt vmcnt(0)
+; GFX942-NEXT: s_setpc_b64 s[30:31]
entry:
tail call void @llvm.memcpy.p1.p4.i64(ptr addrspace(1) noundef nonnull align
1 %dst, ptr addrspace(4) noundef nonnull align 1 %src, i64 16, i1 false)
ret void
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