[llvm-branch-commits] [llvm] [LV] Mask off possibly aliasing vector lanes (PR #100579)

[Sander de Smalen via llvm-branch-commits]

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@@ -5535,6 +5540,11 @@ InstructionCost AArch64TTIImpl::getPartialReductionCost(
   return Cost;
 }
 
+bool AArch64TTIImpl::useSafeEltsMask(ElementCount VF) const {
+  // The whilewr/rw instructions require SVE2
+  return ST->hasSVE2();
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sdesmalen-arm wrote:

This is also supported for SME.

https://github.com/llvm/llvm-project/pull/100579
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