https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/153697
Backport defbbf0129d5c1ac360c6ffd9eaa2f07ab07d622
Requested by: @topperc
>From dcdb0b7d8e7851dbcce9209394256a648a2586f3 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.top...@sifive.com>
Date: Thu, 14 Aug 2025 14:52:54 -0700
Subject: [PATCH] [RISCV][MoveMerge] Don't copy kill flag when moving past an
instruction that reads the register. (#153644)
If we're moving the second copy before another instruction that reads
the copied register, we need to clear the kill flag on the combined
move.
Fixes #153598.
(cherry picked from commit defbbf0129d5c1ac360c6ffd9eaa2f07ab07d622)
---
llvm/lib/Target/RISCV/RISCVMoveMerger.cpp | 16 ++++++++++++++--
llvm/test/CodeGen/RISCV/pr153598.mir | 23 +++++++++++++++++++++++
2 files changed, 37 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/pr153598.mir
diff --git a/llvm/lib/Target/RISCV/RISCVMoveMerger.cpp
b/llvm/lib/Target/RISCV/RISCVMoveMerger.cpp
index 7a2541a652b58..0d37db0138e47 100644
--- a/llvm/lib/Target/RISCV/RISCVMoveMerger.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMoveMerger.cpp
@@ -137,6 +137,11 @@
RISCVMoveMerge::mergePairedInsns(MachineBasicBlock::iterator I,
NextI = next_nodbg(NextI, E);
DebugLoc DL = I->getDebugLoc();
+ // Make a copy so we can update the kill flag in the MoveFromAToS case. The
+ // copied operand needs to be scoped outside the if since we make a pointer
+ // to it.
+ MachineOperand PairedSource = *PairedRegs.Source;
+
// The order of S-reg depends on which instruction holds A0, instead of
// the order of register pair.
// e,g.
@@ -147,8 +152,15 @@
RISCVMoveMerge::mergePairedInsns(MachineBasicBlock::iterator I,
// mv a1, s1 => cm.mva01s s2,s1
bool StartWithX10 = ARegInFirstPair == RISCV::X10;
if (isMoveFromAToS(Opcode)) {
- Sreg1 = StartWithX10 ? FirstPair.Source : PairedRegs.Source;
- Sreg2 = StartWithX10 ? PairedRegs.Source : FirstPair.Source;
+ // We are moving one of the copies earlier so its kill flag may become
+ // invalid. Clear the copied kill flag if there are any reads of the
+ // register between the new location and the old location.
+ for (auto It = std::next(I); It != Paired && PairedSource.isKill(); ++It)
+ if (It->readsRegister(PairedSource.getReg(), TRI))
+ PairedSource.setIsKill(false);
+
+ Sreg1 = StartWithX10 ? FirstPair.Source : &PairedSource;
+ Sreg2 = StartWithX10 ? &PairedSource : FirstPair.Source;
} else {
Sreg1 = StartWithX10 ? FirstPair.Destination : PairedRegs.Destination;
Sreg2 = StartWithX10 ? PairedRegs.Destination : FirstPair.Destination;
diff --git a/llvm/test/CodeGen/RISCV/pr153598.mir
b/llvm/test/CodeGen/RISCV/pr153598.mir
new file mode 100644
index 0000000000000..a084197fe83cc
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/pr153598.mir
@@ -0,0 +1,23 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=riscv32 -mattr=+zcmp -run-pass=riscv-move-merge
-verify-machineinstrs %s -o - | FileCheck %s
+---
+name: mov-merge
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x8, $x9
+ ; CHECK-LABEL: name: mov-merge
+ ; CHECK: liveins: $x8, $x9
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x12 = ADDI $x0, -3
+ ; CHECK-NEXT: SW renamable $x9, $x2, 56
+ ; CHECK-NEXT: CM_MVA01S killed renamable $x9, renamable $x8, implicit-def
$x10, implicit-def $x11
+ ; CHECK-NEXT: SW renamable $x8, $x2, 60
+ ; CHECK-NEXT: PseudoRET
+ $x12 = ADDI $x0, -3
+ SW renamable $x9, $x2, 56
+ $x10 = ADDI killed renamable $x9, 0
+ SW renamable $x8, $x2, 60
+ $x11 = ADDI killed renamable $x8, 0
+ PseudoRET
+...
_______________________________________________
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
