llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-hexagon Author: None (llvmbot) <details> <summary>Changes</summary> Backport 76d993bd25ff462d915f69772454e7b1ca42fdb8 Requested by: @<!-- -->androm3da --- Full diff: https://github.com/llvm/llvm-project/pull/153926.diff 2 Files Affected: - (modified) llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp (+3) - (modified) llvm/test/MC/Hexagon/system-inst.s (+3) ``````````diff diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp index 22cff7c80fa01..bcddb540d35dc 100644 --- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -526,6 +526,9 @@ DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB, MI.insert(MI.begin() + 1, MCOperand::createExpr(MCConstantExpr::create(-1, getContext()))); break; + case Hexagon::Y4_crswap10: + MI.addOperand(MCOperand::createReg(Hexagon::SGP1_0)); + break; default: break; } diff --git a/llvm/test/MC/Hexagon/system-inst.s b/llvm/test/MC/Hexagon/system-inst.s index 7bc1533598532..07f7ca0acb2dc 100644 --- a/llvm/test/MC/Hexagon/system-inst.s +++ b/llvm/test/MC/Hexagon/system-inst.s @@ -89,6 +89,9 @@ crswap(r12,sgp0) #CHECK: 652dc000 { crswap(r13,sgp1) } crswap(r13,sgp1) +#CHECK: 6d8ec000 { crswap(r15:14,s1:0) } +crswap(r15:14,sgp1:0) + #CHECK: 660fc00e { r14 = getimask(r15) } r14=getimask(r15) `````````` </details> https://github.com/llvm/llvm-project/pull/153926 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
