Author: Stephen Long Date: 2025-08-18T07:49:02+02:00 New Revision: 8e0e800222aa555e277a2e0b110ae3a5a52e3e30
URL: https://github.com/llvm/llvm-project/commit/8e0e800222aa555e277a2e0b110ae3a5a52e3e30 DIFF: https://github.com/llvm/llvm-project/commit/8e0e800222aa555e277a2e0b110ae3a5a52e3e30.diff LOG: PreISelIntrinsicLowering: Lower llvm.log to a loop if scalable vec arg (#129744) Similar to ab976a1, but for llvm.log. (cherry picked from commit 19ada02086c371dda75ec9704e50e1e28f1758bb) Added: llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll Modified: llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp llvm/lib/CodeGen/TargetLoweringBase.cpp Removed: ################################################################################ diff --git a/llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp b/llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp index 8de2c48581a1e..9fa96e7372961 100644 --- a/llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp +++ b/llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp @@ -587,12 +587,14 @@ bool PreISelIntrinsicLowering::lowerIntrinsics(Module &M) const { break; case Intrinsic::exp: case Intrinsic::exp2: + case Intrinsic::log: Changed |= forEachCall(F, [&](CallInst *CI) { Type *Ty = CI->getArgOperand(0)->getType(); if (!isa<ScalableVectorType>(Ty)) return false; const TargetLowering *TL = TM->getSubtargetImpl(F)->getTargetLowering(); unsigned Op = TL->IntrinsicIDToISD(F.getIntrinsicID()); + assert(Op != ISD::DELETED_NODE && "unsupported intrinsic"); if (!TL->isOperationExpand(Op, EVT::getEVT(Ty))) return false; return lowerUnaryVectorIntrinsicAsLoop(M, CI); diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp index db2065f878727..ca2a57e9b7b2c 100644 --- a/llvm/lib/CodeGen/TargetLoweringBase.cpp +++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp @@ -1922,6 +1922,8 @@ int TargetLoweringBase::IntrinsicIDToISD(Intrinsic::ID ID) const { return ISD::FEXP; case Intrinsic::exp2: return ISD::FEXP2; + case Intrinsic::log: + return ISD::FLOG; default: return ISD::DELETED_NODE; } diff --git a/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll b/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll new file mode 100644 index 0000000000000..3a1d1324d8e45 --- /dev/null +++ b/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll @@ -0,0 +1,40 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; RUN: opt -passes=pre-isel-intrinsic-lowering -S < %s | FileCheck %s +target triple = "aarch64" + +define <vscale x 4 x float> @scalable_vec_log(<vscale x 4 x float> %input) { +; CHECK-LABEL: define <vscale x 4 x float> @scalable_vec_log( +; CHECK-SAME: <vscale x 4 x float> [[INPUT:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 4 +; CHECK-NEXT: br label %[[BB3:.*]] +; CHECK: [[BB3]]: +; CHECK-NEXT: [[TMP4:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP9:%.*]], %[[BB3]] ] +; CHECK-NEXT: [[TMP5:%.*]] = phi <vscale x 4 x float> [ [[INPUT]], [[TMP0]] ], [ [[TMP8:%.*]], %[[BB3]] ] +; CHECK-NEXT: [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]] +; CHECK-NEXT: [[TMP7:%.*]] = call float @llvm.log.f32(float [[TMP6]]) +; CHECK-NEXT: [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]] +; CHECK-NEXT: [[TMP9]] = add i64 [[TMP4]], 1 +; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]] +; CHECK-NEXT: br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]] +; CHECK: [[BB11]]: +; CHECK-NEXT: ret <vscale x 4 x float> [[TMP8]] +; + %output = call <vscale x 4 x float> @llvm.log.nxv4f32(<vscale x 4 x float> %input) + ret <vscale x 4 x float> %output +} + +define <4 x float> @fixed_vec_log(<4 x float> %input) { +; CHECK-LABEL: define <4 x float> @fixed_vec_log( +; CHECK-SAME: <4 x float> [[INPUT:%.*]]) { +; CHECK-NEXT: [[OUTPUT:%.*]] = call <4 x float> @llvm.log.v4f32(<4 x float> [[INPUT]]) +; CHECK-NEXT: ret <4 x float> [[OUTPUT]] +; + %output = call <4 x float> @llvm.log.v4f32(<4 x float> %input) + ret <4 x float> %output +} + +declare <4 x float> @llvm.log.v4f32(<4 x float>) #0 +declare <vscale x 4 x float> @llvm.log.nxv4f32(<vscale x 4 x float>) #0 + +attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
