Author: Min-Yih Hsu Date: 2025-08-19T09:43:55-07:00 New Revision: f82054eaa214c8b5c33fcae01b212a6b32a135f8
URL: https://github.com/llvm/llvm-project/commit/f82054eaa214c8b5c33fcae01b212a6b32a135f8 DIFF: https://github.com/llvm/llvm-project/commit/f82054eaa214c8b5c33fcae01b212a6b32a135f8.diff LOG: [RISCV] Handle more cases when combining (vfmv.s.f (extract_subvector X, 0)) (#154175) Previously, we fold `(vfmv.s.f (extract_subvector X, 0))` into X when X's type is the same as `vfmv.s.f`'s result type. This patch generalizes it by folding it into insert_subvector when X is narrower and extract_subvector when X is wider. Co-authored-by: Craig Topper <craig.top...@sifive.com> Added: llvm/test/CodeGen/RISCV/rvv/redundant-vfmvsf.ll Modified: llvm/lib/Target/RISCV/RISCVISelLowering.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 3c19cea2bd1dd..4a1db80076530 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -20759,12 +20759,22 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, isNullConstant(Src.getOperand(1)) && Src.getOperand(0).getValueType().isScalableVector()) { EVT VT = N->getValueType(0); - EVT SrcVT = Src.getOperand(0).getValueType(); - assert(SrcVT.getVectorElementType() == VT.getVectorElementType()); + SDValue EVSrc = Src.getOperand(0); + EVT EVSrcVT = EVSrc.getValueType(); + assert(EVSrcVT.getVectorElementType() == VT.getVectorElementType()); // Widths match, just return the original vector. - if (SrcVT == VT) - return Src.getOperand(0); - // TODO: Use insert_subvector/extract_subvector to change widen/narrow? + if (EVSrcVT == VT) + return EVSrc; + SDLoc DL(N); + // Width is narrower, using insert_subvector. + if (EVSrcVT.getVectorMinNumElements() < VT.getVectorMinNumElements()) { + return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), + EVSrc, + DAG.getConstant(0, DL, Subtarget.getXLenVT())); + } + // Width is wider, using extract_subvector. + return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, EVSrc, + DAG.getConstant(0, DL, Subtarget.getXLenVT())); } [[fallthrough]]; } diff --git a/llvm/test/CodeGen/RISCV/rvv/redundant-vfmvsf.ll b/llvm/test/CodeGen/RISCV/rvv/redundant-vfmvsf.ll new file mode 100644 index 0000000000000..da912bf401ec0 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/redundant-vfmvsf.ll @@ -0,0 +1,26 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=riscv64 -mattr='+v,+zvl512b' < %s | FileCheck %s + +define <2 x float> @redundant_vfmv(<2 x float> %arg0, <64 x float> %arg1, <64 x float> %arg2) { +; CHECK-LABEL: redundant_vfmv: +; CHECK: # %bb.0: +; CHECK-NEXT: li a0, 64 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; CHECK-NEXT: vfredusum.vs v9, v12, v8 +; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma +; CHECK-NEXT: vslidedown.vi v8, v8, 1 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; CHECK-NEXT: vfredusum.vs v8, v16, v8 +; CHECK-NEXT: vfmv.f.s fa5, v8 +; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; CHECK-NEXT: vrgather.vi v8, v9, 0 +; CHECK-NEXT: vfslide1down.vf v8, v8, fa5 +; CHECK-NEXT: ret + %s0 = extractelement <2 x float> %arg0, i64 0 + %r0 = tail call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s0, <64 x float> %arg1) + %a0 = insertelement <2 x float> poison, float %r0, i64 0 + %s1 = extractelement <2 x float> %arg0, i64 1 + %r1 = tail call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s1, <64 x float> %arg2) + %a1 = insertelement <2 x float> %a0, float %r1, i64 1 + ret <2 x float> %a1 +} _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
