================ @@ -220,6 +232,7 @@ Changes to the RISC-V Backend * Removed -mattr=+no-rvc-hints that could be used to disable parsing and generation of RVC hints. * Adds assembler support for the Andes `XAndesvsintload` (Andes Vector INT4 Load extension). * Adds assembler support for the Andes `XAndesbfhcvt` (Andes Scalar BFLOAT16 Conversion extension). +* Add combine for shadd family of instructions. ---------------- amy-kwan wrote:
@stefanp-synopsys FYI, we added this to the LLVM 21.x release notes from your patch: [[RISCV] Add combine for shadd family of instructions.](https://github.com/llvm/llvm-project/pull/130829#top) If you don't think this is necessary to add, we can remove this. https://github.com/llvm/llvm-project/pull/154465 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
