llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-loongarch Author: ZhaoQi (zhaoqi5) <details> <summary>Changes</summary> --- Full diff: https://github.com/llvm/llvm-project/pull/158526.diff 8 Files Affected: - (modified) llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td (+8) - (modified) llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td (+8) - (modified) llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr.ll (+1-3) - (modified) llvm/test/CodeGen/LoongArch/lasx/ir-instruction/andn.ll (+4-11) - (modified) llvm/test/CodeGen/LoongArch/lasx/ir-instruction/orn.ll (+12-19) - (modified) llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr.ll (+1-3) - (modified) llvm/test/CodeGen/LoongArch/lsx/ir-instruction/andn.ll (+4-11) - (modified) llvm/test/CodeGen/LoongArch/lsx/ir-instruction/orn.ll (+12-19) ``````````diff diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td index a79c01cbe577a..c851b1b6f5eb7 100644 --- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td @@ -1389,6 +1389,14 @@ def : Pat<(xor (vt LASX256:$xj), (vt LASX256:$xk)), foreach vt = [v32i8, v16i16, v8i32, v4i64] in def : Pat<(vnot (or (vt LASX256:$xj), (vt LASX256:$xk))), (XVNOR_V LASX256:$xj, LASX256:$xk)>; +// XVANDN_V +foreach vt = [v32i8, v16i16, v8i32, v4i64] in +def : Pat<(and (vt (vnot LASX256:$xj)), (vt LASX256:$xk)), + (XVANDN_V LASX256:$xj, LASX256:$xk)>; +// XVORN_V +foreach vt = [v32i8, v16i16, v8i32, v4i64] in +def : Pat<(or (vt LASX256:$xj), (vt (vnot LASX256:$xk))), + (XVORN_V LASX256:$xj, LASX256:$xk)>; // XVANDI_B def : Pat<(and (v32i8 LASX256:$xj), (v32i8 (SplatPat_uimm8 uimm8:$imm))), diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td index eb7120ffb41a6..fe7c47543424b 100644 --- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td @@ -1583,6 +1583,14 @@ def : Pat<(xor (vt LSX128:$vj), (vt LSX128:$vk)), foreach vt = [v16i8, v8i16, v4i32, v2i64] in def : Pat<(vnot (or (vt LSX128:$vj), (vt LSX128:$vk))), (VNOR_V LSX128:$vj, LSX128:$vk)>; +// VANDN_V +foreach vt = [v16i8, v8i16, v4i32, v2i64] in +def : Pat<(and (vt (vnot LSX128:$vj)), (vt LSX128:$vk)), + (VANDN_V LSX128:$vj, LSX128:$vk)>; +// VORN_V +foreach vt = [v16i8, v8i16, v4i32, v2i64] in +def : Pat<(or (vt LSX128:$vj), (vt (vnot LSX128:$vk))), + (VORN_V LSX128:$vj, LSX128:$vk)>; // VANDI_B def : Pat<(and (v16i8 LSX128:$vj), (v16i8 (SplatPat_uimm8 uimm8:$imm))), diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr.ll index 9f148e5a447a5..786233018ad7d 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr.ll @@ -47,9 +47,7 @@ define <4 x i64> @lasx_xvbitclr_d(<4 x i64> %va, <4 x i64> %vb) nounwind { ; LA32-NEXT: xvand.v $xr1, $xr1, $xr2 ; LA32-NEXT: xvrepli.d $xr2, 1 ; LA32-NEXT: xvsll.d $xr1, $xr2, $xr1 -; LA32-NEXT: xvrepli.b $xr2, -1 -; LA32-NEXT: xvxor.v $xr1, $xr1, $xr2 -; LA32-NEXT: xvand.v $xr0, $xr0, $xr1 +; LA32-NEXT: xvandn.v $xr0, $xr1, $xr0 ; LA32-NEXT: ret ; ; LA64-LABEL: lasx_xvbitclr_d: diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/andn.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/andn.ll index ea3b6144805ae..a61d016b8e21e 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/andn.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/andn.ll @@ -7,8 +7,7 @@ define void @andn_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xvld $xr0, $a1, 0 ; CHECK-NEXT: xvld $xr1, $a2, 0 -; CHECK-NEXT: xvxori.b $xr0, $xr0, 255 -; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1 +; CHECK-NEXT: xvandn.v $xr0, $xr0, $xr1 ; CHECK-NEXT: xvst $xr0, $a0, 0 ; CHECK-NEXT: ret entry: @@ -25,9 +24,7 @@ define void @andn_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xvld $xr0, $a1, 0 ; CHECK-NEXT: xvld $xr1, $a2, 0 -; CHECK-NEXT: xvrepli.b $xr2, -1 -; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr2 -; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1 +; CHECK-NEXT: xvandn.v $xr0, $xr0, $xr1 ; CHECK-NEXT: xvst $xr0, $a0, 0 ; CHECK-NEXT: ret entry: @@ -44,9 +41,7 @@ define void @andn_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xvld $xr0, $a1, 0 ; CHECK-NEXT: xvld $xr1, $a2, 0 -; CHECK-NEXT: xvrepli.b $xr2, -1 -; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr2 -; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1 +; CHECK-NEXT: xvandn.v $xr0, $xr0, $xr1 ; CHECK-NEXT: xvst $xr0, $a0, 0 ; CHECK-NEXT: ret entry: @@ -63,9 +58,7 @@ define void @andn_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xvld $xr0, $a1, 0 ; CHECK-NEXT: xvld $xr1, $a2, 0 -; CHECK-NEXT: xvrepli.b $xr2, -1 -; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr2 -; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1 +; CHECK-NEXT: xvandn.v $xr0, $xr0, $xr1 ; CHECK-NEXT: xvst $xr0, $a0, 0 ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/orn.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/orn.ll index 5115fa880271d..e0f72ebc62445 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/orn.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/orn.ll @@ -5,10 +5,9 @@ define void @orn_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { ; CHECK-LABEL: orn_v32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a2, 0 -; CHECK-NEXT: xvld $xr1, $a1, 0 -; CHECK-NEXT: xvxori.b $xr0, $xr0, 255 -; CHECK-NEXT: xvor.v $xr0, $xr1, $xr0 +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvld $xr1, $a2, 0 +; CHECK-NEXT: xvorn.v $xr0, $xr0, $xr1 ; CHECK-NEXT: xvst $xr0, $a0, 0 ; CHECK-NEXT: ret entry: @@ -23,11 +22,9 @@ entry: define void @orn_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind { ; CHECK-LABEL: orn_v16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a2, 0 -; CHECK-NEXT: xvld $xr1, $a1, 0 -; CHECK-NEXT: xvrepli.b $xr2, -1 -; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr2 -; CHECK-NEXT: xvor.v $xr0, $xr1, $xr0 +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvld $xr1, $a2, 0 +; CHECK-NEXT: xvorn.v $xr0, $xr0, $xr1 ; CHECK-NEXT: xvst $xr0, $a0, 0 ; CHECK-NEXT: ret entry: @@ -42,11 +39,9 @@ entry: define void @orn_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind { ; CHECK-LABEL: orn_v8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a2, 0 -; CHECK-NEXT: xvld $xr1, $a1, 0 -; CHECK-NEXT: xvrepli.b $xr2, -1 -; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr2 -; CHECK-NEXT: xvor.v $xr0, $xr1, $xr0 +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvld $xr1, $a2, 0 +; CHECK-NEXT: xvorn.v $xr0, $xr0, $xr1 ; CHECK-NEXT: xvst $xr0, $a0, 0 ; CHECK-NEXT: ret entry: @@ -61,11 +56,9 @@ entry: define void @orn_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind { ; CHECK-LABEL: orn_v4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a2, 0 -; CHECK-NEXT: xvld $xr1, $a1, 0 -; CHECK-NEXT: xvrepli.b $xr2, -1 -; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr2 -; CHECK-NEXT: xvor.v $xr0, $xr1, $xr0 +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvld $xr1, $a2, 0 +; CHECK-NEXT: xvorn.v $xr0, $xr0, $xr1 ; CHECK-NEXT: xvst $xr0, $a0, 0 ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr.ll index ac0eca2fc33ea..438004d2d52db 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr.ll @@ -47,9 +47,7 @@ define <2 x i64> @lsx_vbitclr_d(<2 x i64> %va, <2 x i64> %vb) nounwind { ; LA32-NEXT: vand.v $vr1, $vr1, $vr2 ; LA32-NEXT: vrepli.d $vr2, 1 ; LA32-NEXT: vsll.d $vr1, $vr2, $vr1 -; LA32-NEXT: vrepli.b $vr2, -1 -; LA32-NEXT: vxor.v $vr1, $vr1, $vr2 -; LA32-NEXT: vand.v $vr0, $vr0, $vr1 +; LA32-NEXT: vandn.v $vr0, $vr1, $vr0 ; LA32-NEXT: ret ; ; LA64-LABEL: lsx_vbitclr_d: diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/andn.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/andn.ll index 4b6a77919659b..c1ba98c5dd146 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/andn.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/andn.ll @@ -7,8 +7,7 @@ define void @andn_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vld $vr0, $a1, 0 ; CHECK-NEXT: vld $vr1, $a2, 0 -; CHECK-NEXT: vxori.b $vr0, $vr0, 255 -; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vandn.v $vr0, $vr0, $vr1 ; CHECK-NEXT: vst $vr0, $a0, 0 ; CHECK-NEXT: ret entry: @@ -25,9 +24,7 @@ define void @andn_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vld $vr0, $a1, 0 ; CHECK-NEXT: vld $vr1, $a2, 0 -; CHECK-NEXT: vrepli.b $vr2, -1 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr2 -; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vandn.v $vr0, $vr0, $vr1 ; CHECK-NEXT: vst $vr0, $a0, 0 ; CHECK-NEXT: ret entry: @@ -44,9 +41,7 @@ define void @andn_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vld $vr0, $a1, 0 ; CHECK-NEXT: vld $vr1, $a2, 0 -; CHECK-NEXT: vrepli.b $vr2, -1 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr2 -; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vandn.v $vr0, $vr0, $vr1 ; CHECK-NEXT: vst $vr0, $a0, 0 ; CHECK-NEXT: ret entry: @@ -63,9 +58,7 @@ define void @andn_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vld $vr0, $a1, 0 ; CHECK-NEXT: vld $vr1, $a2, 0 -; CHECK-NEXT: vrepli.b $vr2, -1 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr2 -; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vandn.v $vr0, $vr0, $vr1 ; CHECK-NEXT: vst $vr0, $a0, 0 ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/orn.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/orn.ll index 524dfd616fa3b..bb1be34aebcab 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/orn.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/orn.ll @@ -5,10 +5,9 @@ define void @orn_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind { ; CHECK-LABEL: orn_v16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vld $vr0, $a2, 0 -; CHECK-NEXT: vld $vr1, $a1, 0 -; CHECK-NEXT: vxori.b $vr0, $vr0, 255 -; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vld $vr1, $a2, 0 +; CHECK-NEXT: vorn.v $vr0, $vr0, $vr1 ; CHECK-NEXT: vst $vr0, $a0, 0 ; CHECK-NEXT: ret entry: @@ -23,11 +22,9 @@ entry: define void @orn_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind { ; CHECK-LABEL: orn_v8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vld $vr0, $a2, 0 -; CHECK-NEXT: vld $vr1, $a1, 0 -; CHECK-NEXT: vrepli.b $vr2, -1 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr2 -; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vld $vr1, $a2, 0 +; CHECK-NEXT: vorn.v $vr0, $vr0, $vr1 ; CHECK-NEXT: vst $vr0, $a0, 0 ; CHECK-NEXT: ret entry: @@ -42,11 +39,9 @@ entry: define void @orn_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind { ; CHECK-LABEL: orn_v4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vld $vr0, $a2, 0 -; CHECK-NEXT: vld $vr1, $a1, 0 -; CHECK-NEXT: vrepli.b $vr2, -1 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr2 -; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vld $vr1, $a2, 0 +; CHECK-NEXT: vorn.v $vr0, $vr0, $vr1 ; CHECK-NEXT: vst $vr0, $a0, 0 ; CHECK-NEXT: ret entry: @@ -61,11 +56,9 @@ entry: define void @orn_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind { ; CHECK-LABEL: orn_v2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vld $vr0, $a2, 0 -; CHECK-NEXT: vld $vr1, $a1, 0 -; CHECK-NEXT: vrepli.b $vr2, -1 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr2 -; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vld $vr1, $a2, 0 +; CHECK-NEXT: vorn.v $vr0, $vr0, $vr1 ; CHECK-NEXT: vst $vr0, $a0, 0 ; CHECK-NEXT: ret entry: `````````` </details> https://github.com/llvm/llvm-project/pull/158526 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
