https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/159370
The operand constraints already express this constraint, and
InstrEmitter will respect them.
>From 257ef69737087efe560c067660a32182ab827e03 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <matthew.arsena...@amd.com>
Date: Wed, 17 Sep 2025 23:19:39 +0900
Subject: [PATCH] AMDGPU: Remove unnecessary operand legalization for WMMAs
The operand constraints already express this constraint, and
InstrEmitter will respect them.
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 15 ---------------
1 file changed, 15 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 37c75fe7f7dfd..a737ad98c1d80 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -6547,21 +6547,6 @@ void
SIInstrInfo::legalizeOperandsVOP3(MachineRegisterInfo &MRI,
!RI.isVGPR(MRI, MI.getOperand(VOP3Idx[2]).getReg()))
legalizeOpWithMove(MI, VOP3Idx[2]);
- if (isWMMA(MI)) {
- // scale_src has a register class restricted to low 256 VGPRs, we may need
- // to insert a copy to the restricted VGPR class.
- int ScaleSrc0Idx =
- AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::scale_src0);
- if (ScaleSrc0Idx != -1) {
- int ScaleSrc1Idx =
- AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::scale_src1);
- if (!isOperandLegal(MI, ScaleSrc0Idx))
- legalizeOpWithMove(MI, ScaleSrc0Idx);
- if (!isOperandLegal(MI, ScaleSrc1Idx))
- legalizeOpWithMove(MI, ScaleSrc1Idx);
- }
- }
-
// Fix the register class of packed FP32 instructions on gfx12+. See
// SIInstrInfo::isLegalGFX12PlusPackedMathFP32Operand for more information.
if (AMDGPU::isPackedFP32Inst(Opc) && AMDGPU::isGFX12Plus(ST)) {
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