https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/158246
This is special for the same reason av_mov_b64_imm_pseudo is special. >From e5032294b4979c4b7f2367cee30c24d42901714b Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Fri, 5 Sep 2025 17:27:37 +0900 Subject: [PATCH] AMDGPU: Move spill pseudo special case out of adjustAllocatableRegClass This is special for the same reason av_mov_b64_imm_pseudo is special. --- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 8 +++----- llvm/lib/Target/AMDGPU/SIInstrInfo.h | 6 ++++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 5c3340703ba3b..b1a61886802f4 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -5976,8 +5976,7 @@ SIInstrInfo::getWholeWaveFunctionSetup(MachineFunction &MF) const { static const TargetRegisterClass * adjustAllocatableRegClass(const GCNSubtarget &ST, const SIRegisterInfo &RI, const MCInstrDesc &TID, unsigned RCID) { - if (!ST.hasGFX90AInsts() && (((TID.mayLoad() || TID.mayStore()) && - !(TID.TSFlags & SIInstrFlags::Spill)))) { + if (!ST.hasGFX90AInsts() && (((TID.mayLoad() || TID.mayStore())))) { switch (RCID) { case AMDGPU::AV_32RegClassID: RCID = AMDGPU::VGPR_32RegClassID; @@ -6012,10 +6011,9 @@ const TargetRegisterClass *SIInstrInfo::getRegClass(const MCInstrDesc &TID, if (OpNum >= TID.getNumOperands()) return nullptr; auto RegClass = TID.operands()[OpNum].RegClass; - if (TID.getOpcode() == AMDGPU::AV_MOV_B64_IMM_PSEUDO) { - // Special pseudos have no alignment requirement + // Special pseudos have no alignment requirement + if (TID.getOpcode() == AMDGPU::AV_MOV_B64_IMM_PSEUDO || isSpill(TID)) return RI.getRegClass(RegClass); - } return adjustAllocatableRegClass(ST, RI, TID, RegClass); } diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h index f7dde2b90b68e..e0373e7768435 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -797,10 +797,12 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo { return get(Opcode).TSFlags & SIInstrFlags::Spill; } - static bool isSpill(const MachineInstr &MI) { - return MI.getDesc().TSFlags & SIInstrFlags::Spill; + static bool isSpill(const MCInstrDesc &Desc) { + return Desc.TSFlags & SIInstrFlags::Spill; } + static bool isSpill(const MachineInstr &MI) { return isSpill(MI.getDesc()); } + static bool isWWMRegSpillOpcode(uint16_t Opcode) { return Opcode == AMDGPU::SI_SPILL_WWM_V32_SAVE || Opcode == AMDGPU::SI_SPILL_WWM_AV32_SAVE || _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
