llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-sparc Author: Matt Arsenault (arsenm) <details> <summary>Changes</summary> --- Full diff: https://github.com/llvm/llvm-project/pull/158271.diff 2 Files Affected: - (modified) llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp (-8) - (modified) llvm/lib/Target/Sparc/SparcInstrInfo.td (+19-2) ``````````diff diff --git a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp index c3d60f3689e1f..e585e5af42d32 100644 --- a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp +++ b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp @@ -159,14 +159,6 @@ static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst, unsigned RegNo, return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder); } -// This is used for the type "ptr_rc", which is either IntRegs or I64Regs -// depending on SparcRegisterInfo::getPointerRegClass. -static DecodeStatus DecodePointerLikeRegClass0(MCInst &Inst, unsigned RegNo, - uint64_t Address, - const MCDisassembler *Decoder) { - return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder); -} - static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder) { diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td index 53972d6c105a4..97e7fd7769edb 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.td +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -95,10 +95,27 @@ def HasFSMULD : Predicate<"!Subtarget->hasNoFSMULD()">; // will pick deprecated instructions. def UseDeprecatedInsts : Predicate<"Subtarget->useV8DeprecatedInsts()">; +//===----------------------------------------------------------------------===// +// HwModes Pattern Stuff +//===----------------------------------------------------------------------===// + +defvar SPARC32 = DefaultMode; +def SPARC64 : HwMode<[Is64Bit]>; + //===----------------------------------------------------------------------===// // Instruction Pattern Stuff //===----------------------------------------------------------------------===// +def sparc_ptr_rc : RegClassByHwMode< + [SPARC32, SPARC64], + [IntRegs, I64Regs]>; + +// Both cases can use the same decoder method, so avoid the dispatch +// by hwmode by setting an explicit DecoderMethod +def ptr_op : RegisterOperand<sparc_ptr_rc> { + let DecoderMethod = "DecodeIntRegsRegisterClass"; +} + // FIXME these should have AsmOperandClass. def uimm3 : PatLeaf<(imm), [{ return isUInt<3>(N->getZExtValue()); }]>; @@ -178,12 +195,12 @@ def simm13Op : Operand<iPTR> { def MEMrr : Operand<iPTR> { let PrintMethod = "printMemOperand"; - let MIOperandInfo = (ops ptr_rc, ptr_rc); + let MIOperandInfo = (ops ptr_op, ptr_op); let ParserMatchClass = SparcMEMrrAsmOperand; } def MEMri : Operand<iPTR> { let PrintMethod = "printMemOperand"; - let MIOperandInfo = (ops ptr_rc, simm13Op); + let MIOperandInfo = (ops ptr_op, simm13Op); let ParserMatchClass = SparcMEMriAsmOperand; } `````````` </details> https://github.com/llvm/llvm-project/pull/158271 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
