https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/161792
This is trying to constrain the register class of a physical register, which makes no sense. >From cf04ae0c7c664d2fba2995eae7ce825fa4badd95 Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Fri, 3 Oct 2025 14:29:14 +0900 Subject: [PATCH] AMDGPU: Stop trying to constrain register class of post-RA-pseudos This is trying to constrain the register class of a physical register, which makes no sense. --- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 2 -- 1 file changed, 2 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index fe6b8b96cbd57..cda8069936af2 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -2112,8 +2112,6 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { case AMDGPU::SI_RESTORE_S32_FROM_VGPR: MI.setDesc(get(AMDGPU::V_READLANE_B32)); - MI.getMF()->getRegInfo().constrainRegClass(MI.getOperand(0).getReg(), - &AMDGPU::SReg_32_XM0RegClass); break; case AMDGPU::AV_MOV_B32_IMM_PSEUDO: { Register Dst = MI.getOperand(0).getReg(); _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
