https://github.com/jthackray updated https://github.com/llvm/llvm-project/pull/163162
>From 3aabdd283f382cd60f994a6a9e261557e91d4592 Mon Sep 17 00:00:00 2001 From: Jonathan Thackray <[email protected]> Date: Fri, 5 Sep 2025 23:47:55 +0100 Subject: [PATCH 1/2] [AArch64][llvm] Armv9.7-A: Add support for SVE2p3 CVT operations Add instructions for SVE2p3 CVT operations: - FCVTZSN - FCVTZUN - SCVTF - SCVTFLT - UCVTF - UCVTFLT as documented here: * https://developer.arm.com/documentation/ddi0602/2025-09/ * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions --- .../lib/Target/AArch64/AArch64SVEInstrInfo.td | 9 + llvm/lib/Target/AArch64/SVEInstrFormats.td | 46 +++++ .../MC/AArch64/SVE2p3/fcvtz-diagnostics.s | 55 ++++++ llvm/test/MC/AArch64/SVE2p3/fcvtz.s | 165 ++++++++++++++++++ .../MC/AArch64/SVE2p3/scvtf-diagnostics.s | 65 +++++++ llvm/test/MC/AArch64/SVE2p3/scvtf.s | 93 ++++++++++ .../MC/AArch64/SVE2p3/ucvtf-diagnostics.s | 65 +++++++ llvm/test/MC/AArch64/SVE2p3/ucvtf.s | 93 ++++++++++ 8 files changed, 591 insertions(+) create mode 100644 llvm/test/MC/AArch64/SVE2p3/fcvtz-diagnostics.s create mode 100644 llvm/test/MC/AArch64/SVE2p3/fcvtz.s create mode 100644 llvm/test/MC/AArch64/SVE2p3/scvtf-diagnostics.s create mode 100644 llvm/test/MC/AArch64/SVE2p3/scvtf.s create mode 100644 llvm/test/MC/AArch64/SVE2p3/ucvtf-diagnostics.s create mode 100644 llvm/test/MC/AArch64/SVE2p3/ucvtf.s diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 2607a5d0c53a1..dfb7bd348e0e0 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -4639,6 +4639,15 @@ let Predicates = [HasSVE2p3_or_SME2p3] in { def SDOT_ZZZI_BtoH : sve_intx_dot_by_indexed_elem_x<0b0, "sdot">; def UDOT_ZZZI_BtoH : sve_intx_dot_by_indexed_elem_x<0b1, "udot">; + // SVE2 fp convert, narrow and interleave to integer, rounding toward zero + defm FCVTZSN_Z2Z : sve2_fp_to_int_downcvt<"fcvtzsn", 0b0>; + defm FCVTZUN_Z2Z : sve2_fp_to_int_downcvt<"fcvtzun", 0b1>; + + // SVE2 signed/unsigned integer convert to floating-point + defm SCVTF_ZZ : sve2_int_to_fp_upcvt<"scvtf", 0b00>; + defm SCVTFLT_ZZ : sve2_int_to_fp_upcvt<"scvtflt", 0b10>; + defm UCVTF_ZZ : sve2_int_to_fp_upcvt<"ucvtf", 0b01>; + defm UCVTFLT_ZZ : sve2_int_to_fp_upcvt<"ucvtflt", 0b11>; } // End HasSME2p3orSVE2p3 //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 21b9310f69159..3255d8e6cbe74 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -11300,3 +11300,49 @@ class sve_int_mla_cpa<string asm> let ElementSize = ZPR64.ElementSize; } + +//===----------------------------------------------------------------------===// +// FCVTZSN +//===----------------------------------------------------------------------===// +class sve2_fp_to_int_downcvt<string asm, ZPRRegOp ZdRC, RegisterOperand ZSrcOp, bits<2> size, bit U> + : I<(outs ZdRC:$Zd), (ins ZSrcOp:$Zn), + asm, "\t$Zd, $Zn", "", []>, Sched<[]> { + bits<5> Zd; + bits<4> Zn; + let Inst{31-24} = 0b01100101; + let Inst{23-22} = size; + let Inst{21-11} = 0b00110100110; + let Inst{10} = U; + let Inst{9-6} = Zn; + let Inst{5} = 0b0; + let Inst{4-0} = Zd; +} + +multiclass sve2_fp_to_int_downcvt<string asm, bit U> { + def _HtoB : sve2_fp_to_int_downcvt<asm, ZPR8, ZZ_h_mul_r, 0b01, U>; + def _StoH : sve2_fp_to_int_downcvt<asm, ZPR16, ZZ_s_mul_r, 0b10, U>; + def _DtoS : sve2_fp_to_int_downcvt<asm, ZPR32, ZZ_d_mul_r, 0b11, U>; +} + +//===----------------------------------------------------------------------===// +// SCVTF +//===----------------------------------------------------------------------===// +class sve2_int_to_fp_upcvt<string asm, ZPRRegOp ZdRC, ZPRRegOp ZnRC, + bits<2> size, bits<2> U> + : I<(outs ZdRC:$Zd), (ins ZnRC:$Zn), + asm, "\t$Zd, $Zn", "", []>, Sched<[]> { + bits<5> Zd; + bits<5> Zn; + let Inst{31-24} = 0b01100101; + let Inst{23-22} = size; + let Inst{21-12} = 0b0011000011; + let Inst{11-10} = U; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve2_int_to_fp_upcvt<string asm, bits<2> U> { + def _BtoH : sve2_int_to_fp_upcvt<asm, ZPR16, ZPR8, 0b01, U>; + def _HtoS : sve2_int_to_fp_upcvt<asm, ZPR32, ZPR16, 0b10, U>; + def _StoD : sve2_int_to_fp_upcvt<asm, ZPR64, ZPR32, 0b11, U>; +} diff --git a/llvm/test/MC/AArch64/SVE2p3/fcvtz-diagnostics.s b/llvm/test/MC/AArch64/SVE2p3/fcvtz-diagnostics.s new file mode 100644 index 0000000000000..bd182e8713e18 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p3/fcvtz-diagnostics.s @@ -0,0 +1,55 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid operand for instruction + +fcvtzsn z0.b, { z0.b, z1.b } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvtzsn z0.b, { z0.b, z1.b } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtzsn z0.h, { z0.h, z1.h } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvtzsn z0.h, { z0.h, z1.h } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtzsn z0.s, { z0.s, z1.s } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvtzsn z0.s, { z0.s, z1.s } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +fcvtzsn z0.b, { z0.h, z1.h } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvtzsn z0.b, { z0.h, z1.h } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid operand for instruction + +fcvtzun z0.b, { z0.b, z1.b } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvtzun z0.b, { z0.b, z1.b } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtzun z0.h, { z0.h, z1.h } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvtzun z0.h, { z0.h, z1.h } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtzun z0.s, { z0.s, z1.s } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvtzun z0.s, { z0.s, z1.s } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +fcvtzun z0.b, { z0.h, z1.h } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvtzun z0.b, { z0.h, z1.h } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p3/fcvtz.s b/llvm/test/MC/AArch64/SVE2p3/fcvtz.s new file mode 100644 index 0000000000000..af01f348e71b1 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p3/fcvtz.s @@ -0,0 +1,165 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p3 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p3 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p3 < %s \ +// RUN: | llvm-objdump -d --mattr=-sve2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p3 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +// ------------------------------------------------------------- +// Floating-point convert, narrow and interleave to signed integer, rounding toward zero + +fcvtzsn z0.b, { z0.h, z1.h } +// CHECK-INST: fcvtzsn z0.b, { z0.h, z1.h } +// CHECK-ENCODING: encoding: [0x00,0x30,0x4d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654d3000 <unknown> + +fcvtzsn z31.b, { z0.h, z1.h } +// CHECK-INST: fcvtzsn z31.b, { z0.h, z1.h } +// CHECK-ENCODING: encoding: [0x1f,0x30,0x4d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654d301f <unknown> + +fcvtzsn z0.b, { z30.h, z31.h } +// CHECK-INST: fcvtzsn z0.b, { z30.h, z31.h } +// CHECK-ENCODING: encoding: [0xc0,0x33,0x4d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654d33c0 <unknown> + +fcvtzsn z31.b, { z30.h, z31.h } +// CHECK-INST: fcvtzsn z31.b, { z30.h, z31.h } +// CHECK-ENCODING: encoding: [0xdf,0x33,0x4d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654d33df <unknown> + +fcvtzsn z0.h, { z0.s, z1.s } +// CHECK-INST: fcvtzsn z0.h, { z0.s, z1.s } +// CHECK-ENCODING: encoding: [0x00,0x30,0x8d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658d3000 <unknown> + +fcvtzsn z31.h, { z0.s, z1.s } +// CHECK-INST: fcvtzsn z31.h, { z0.s, z1.s } +// CHECK-ENCODING: encoding: [0x1f,0x30,0x8d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658d301f <unknown> + +fcvtzsn z0.h, { z30.s, z31.s } +// CHECK-INST: fcvtzsn z0.h, { z30.s, z31.s } +// CHECK-ENCODING: encoding: [0xc0,0x33,0x8d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658d33c0 <unknown> + +fcvtzsn z31.h, { z30.s, z31.s } +// CHECK-INST: fcvtzsn z31.h, { z30.s, z31.s } +// CHECK-ENCODING: encoding: [0xdf,0x33,0x8d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658d33df <unknown> + +fcvtzsn z0.s, { z0.d, z1.d } +// CHECK-INST: fcvtzsn z0.s, { z0.d, z1.d } +// CHECK-ENCODING: encoding: [0x00,0x30,0xcd,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cd3000 <unknown> + +fcvtzsn z31.s, { z0.d, z1.d } +// CHECK-INST: fcvtzsn z31.s, { z0.d, z1.d } +// CHECK-ENCODING: encoding: [0x1f,0x30,0xcd,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cd301f <unknown> + +fcvtzsn z0.s, { z30.d, z31.d } +// CHECK-INST: fcvtzsn z0.s, { z30.d, z31.d } +// CHECK-ENCODING: encoding: [0xc0,0x33,0xcd,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cd33c0 <unknown> + +fcvtzsn z31.s, { z30.d, z31.d } +// CHECK-INST: fcvtzsn z31.s, { z30.d, z31.d } +// CHECK-ENCODING: encoding: [0xdf,0x33,0xcd,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cd33df <unknown> + +// ------------------------------------------------------------- +// Floating-point convert, narrow and interleave to unsigned integer, rounding toward zero + +fcvtzun z0.b, { z0.h, z1.h } +// CHECK-INST: fcvtzun z0.b, { z0.h, z1.h } +// CHECK-ENCODING: encoding: [0x00,0x34,0x4d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654d3400 <unknown> + +fcvtzun z31.b, { z0.h, z1.h } +// CHECK-INST: fcvtzun z31.b, { z0.h, z1.h } +// CHECK-ENCODING: encoding: [0x1f,0x34,0x4d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654d341f <unknown> + +fcvtzun z0.b, { z30.h, z31.h } +// CHECK-INST: fcvtzun z0.b, { z30.h, z31.h } +// CHECK-ENCODING: encoding: [0xc0,0x37,0x4d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654d37c0 <unknown> + +fcvtzun z31.b, { z30.h, z31.h } +// CHECK-INST: fcvtzun z31.b, { z30.h, z31.h } +// CHECK-ENCODING: encoding: [0xdf,0x37,0x4d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654d37df <unknown> + +fcvtzun z0.h, { z0.s, z1.s } +// CHECK-INST: fcvtzun z0.h, { z0.s, z1.s } +// CHECK-ENCODING: encoding: [0x00,0x34,0x8d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658d3400 <unknown> + +fcvtzun z31.h, { z0.s, z1.s } +// CHECK-INST: fcvtzun z31.h, { z0.s, z1.s } +// CHECK-ENCODING: encoding: [0x1f,0x34,0x8d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658d341f <unknown> + +fcvtzun z0.h, { z30.s, z31.s } +// CHECK-INST: fcvtzun z0.h, { z30.s, z31.s } +// CHECK-ENCODING: encoding: [0xc0,0x37,0x8d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658d37c0 <unknown> + +fcvtzun z31.h, { z30.s, z31.s } +// CHECK-INST: fcvtzun z31.h, { z30.s, z31.s } +// CHECK-ENCODING: encoding: [0xdf,0x37,0x8d,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658d37df <unknown> + +fcvtzun z0.s, { z0.d, z1.d } +// CHECK-INST: fcvtzun z0.s, { z0.d, z1.d } +// CHECK-ENCODING: encoding: [0x00,0x34,0xcd,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cd3400 <unknown> + +fcvtzun z31.s, { z0.d, z1.d } +// CHECK-INST: fcvtzun z31.s, { z0.d, z1.d } +// CHECK-ENCODING: encoding: [0x1f,0x34,0xcd,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cd341f <unknown> + +fcvtzun z0.s, { z30.d, z31.d } +// CHECK-INST: fcvtzun z0.s, { z30.d, z31.d } +// CHECK-ENCODING: encoding: [0xc0,0x37,0xcd,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cd37c0 <unknown> + +fcvtzun z31.s, { z30.d, z31.d } +// CHECK-INST: fcvtzun z31.s, { z30.d, z31.d } +// CHECK-ENCODING: encoding: [0xdf,0x37,0xcd,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cd37df <unknown> diff --git a/llvm/test/MC/AArch64/SVE2p3/scvtf-diagnostics.s b/llvm/test/MC/AArch64/SVE2p3/scvtf-diagnostics.s new file mode 100644 index 0000000000000..add25d926a55d --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p3/scvtf-diagnostics.s @@ -0,0 +1,65 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid element width + +scvtf z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: scvtf z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +scvtf z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: scvtf z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +scvtf z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: scvtf z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +scvtf z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: scvtf z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +scvtf z0.h, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: scvtf z0.h, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +scvtflt z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: scvtflt z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +scvtflt z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: scvtflt z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +scvtflt z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: scvtflt z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +scvtflt z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: scvtflt z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +scvtflt z0.h, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: scvtflt z0.h, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p3/scvtf.s b/llvm/test/MC/AArch64/SVE2p3/scvtf.s new file mode 100644 index 0000000000000..2d6b71355c1f3 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p3/scvtf.s @@ -0,0 +1,93 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p3 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p3 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p3 < %s \ +// RUN: | llvm-objdump -d --mattr=-sve2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p3 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +// ----------------------------------------------------------------------- +// Signed integer convert to floating-point (bottom, unpredicated) + +scvtf z0.h, z0.b +// CHECK-INST: scvtf z0.h, z0.b +// CHECK-ENCODING: encoding: [0x00,0x30,0x4c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654c3000 <unknown> + +scvtf z31.h, z31.b +// CHECK-INST: scvtf z31.h, z31.b +// CHECK-ENCODING: encoding: [0xff,0x33,0x4c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654c33ff <unknown> + +scvtf z0.s, z0.h +// CHECK-INST: scvtf z0.s, z0.h +// CHECK-ENCODING: encoding: [0x00,0x30,0x8c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658c3000 <unknown> + +scvtf z31.s, z31.h +// CHECK-INST: scvtf z31.s, z31.h +// CHECK-ENCODING: encoding: [0xff,0x33,0x8c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658c33ff <unknown> + +scvtf z0.d, z0.s +// CHECK-INST: scvtf z0.d, z0.s +// CHECK-ENCODING: encoding: [0x00,0x30,0xcc,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cc3000 <unknown> + +scvtf z31.d, z31.s +// CHECK-INST: scvtf z31.d, z31.s +// CHECK-ENCODING: encoding: [0xff,0x33,0xcc,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cc33ff <unknown> + +// ----------------------------------------------------------------------- +// Signed integer convert to floating-point (top, unpredicated) + +scvtflt z0.h, z0.b +// CHECK-INST: scvtflt z0.h, z0.b +// CHECK-ENCODING: encoding: [0x00,0x38,0x4c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654c3800 <unknown> + +scvtflt z31.h, z31.b +// CHECK-INST: scvtflt z31.h, z31.b +// CHECK-ENCODING: encoding: [0xff,0x3b,0x4c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654c3bff <unknown> + +scvtflt z0.s, z0.h +// CHECK-INST: scvtflt z0.s, z0.h +// CHECK-ENCODING: encoding: [0x00,0x38,0x8c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658c3800 <unknown> + +scvtflt z31.s, z31.h +// CHECK-INST: scvtflt z31.s, z31.h +// CHECK-ENCODING: encoding: [0xff,0x3b,0x8c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658c3bff <unknown> + +scvtflt z0.d, z0.s +// CHECK-INST: scvtflt z0.d, z0.s +// CHECK-ENCODING: encoding: [0x00,0x38,0xcc,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cc3800 <unknown> + +scvtflt z31.d, z31.s +// CHECK-INST: scvtflt z31.d, z31.s +// CHECK-ENCODING: encoding: [0xff,0x3b,0xcc,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cc3bff <unknown> diff --git a/llvm/test/MC/AArch64/SVE2p3/ucvtf-diagnostics.s b/llvm/test/MC/AArch64/SVE2p3/ucvtf-diagnostics.s new file mode 100644 index 0000000000000..49c798f9298dd --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p3/ucvtf-diagnostics.s @@ -0,0 +1,65 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid element width + +ucvtf z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ucvtf z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ucvtf z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ucvtf z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ucvtf z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ucvtf z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ucvtf z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ucvtf z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +ucvtf z0.h, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ucvtf z0.h, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +ucvtflt z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ucvtflt z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ucvtflt z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ucvtflt z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ucvtflt z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ucvtflt z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ucvtflt z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ucvtflt z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +ucvtflt z0.h, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ucvtflt z0.h, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p3/ucvtf.s b/llvm/test/MC/AArch64/SVE2p3/ucvtf.s new file mode 100644 index 0000000000000..a34c58066433f --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p3/ucvtf.s @@ -0,0 +1,93 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p3 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p3 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p3 < %s \ +// RUN: | llvm-objdump -d --mattr=-sve2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p3 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +// ----------------------------------------------------------------------- +// Unsigned integer convert to floating-point (bottom, unpredicated) + +ucvtf z0.h, z0.b +// CHECK-INST: ucvtf z0.h, z0.b +// CHECK-ENCODING: encoding: [0x00,0x34,0x4c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654c3400 <unknown> + +ucvtf z31.h, z31.b +// CHECK-INST: ucvtf z31.h, z31.b +// CHECK-ENCODING: encoding: [0xff,0x37,0x4c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654c37ff <unknown> + +ucvtf z0.s, z0.h +// CHECK-INST: ucvtf z0.s, z0.h +// CHECK-ENCODING: encoding: [0x00,0x34,0x8c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658c3400 <unknown> + +ucvtf z31.s, z31.h +// CHECK-INST: ucvtf z31.s, z31.h +// CHECK-ENCODING: encoding: [0xff,0x37,0x8c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658c37ff <unknown> + +ucvtf z0.d, z0.s +// CHECK-INST: ucvtf z0.d, z0.s +// CHECK-ENCODING: encoding: [0x00,0x34,0xcc,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cc3400 <unknown> + +ucvtf z31.d, z31.s +// CHECK-INST: ucvtf z31.d, z31.s +// CHECK-ENCODING: encoding: [0xff,0x37,0xcc,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cc37ff <unknown> + +// ----------------------------------------------------------------------- +// Unsigned integer convert to floating-point (top, unpredicated) + +ucvtflt z0.h, z0.b +// CHECK-INST: ucvtflt z0.h, z0.b +// CHECK-ENCODING: encoding: [0x00,0x3c,0x4c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654c3c00 <unknown> + +ucvtflt z31.h, z31.b +// CHECK-INST: ucvtflt z31.h, z31.b +// CHECK-ENCODING: encoding: [0xff,0x3f,0x4c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654c3fff <unknown> + +ucvtflt z0.s, z0.h +// CHECK-INST: ucvtflt z0.s, z0.h +// CHECK-ENCODING: encoding: [0x00,0x3c,0x8c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658c3c00 <unknown> + +ucvtflt z31.s, z31.h +// CHECK-INST: ucvtflt z31.s, z31.h +// CHECK-ENCODING: encoding: [0xff,0x3f,0x8c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658c3fff <unknown> + +ucvtflt z0.d, z0.s +// CHECK-INST: ucvtflt z0.d, z0.s +// CHECK-ENCODING: encoding: [0x00,0x3c,0xcc,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cc3c00 <unknown> + +ucvtflt z31.d, z31.s +// CHECK-INST: ucvtflt z31.d, z31.s +// CHECK-ENCODING: encoding: [0xff,0x3f,0xcc,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cc3fff <unknown> >From 1a80ed815386fae47a337ffa757f63a0f1b59302 Mon Sep 17 00:00:00 2001 From: Jonathan Thackray <[email protected]> Date: Thu, 16 Oct 2025 15:03:39 +0100 Subject: [PATCH 2/2] fixup! [AArch64][llvm] Armv9.7-A: Add support for SVE2p3 CVT operations CR suggestions: - improve comments - combine positive and negative testcases into 2 files - add tests for fcvtzsn if Zd is a multiple of 2 --- llvm/lib/Target/AArch64/SVEInstrFormats.td | 4 +- llvm/test/MC/AArch64/SVE2p3/cvt-diagnostics.s | 193 ++++++++++++++++++ .../test/MC/AArch64/SVE2p3/{fcvtz.s => cvt.s} | 171 ++++++++++++++++ .../MC/AArch64/SVE2p3/fcvtz-diagnostics.s | 55 ----- .../MC/AArch64/SVE2p3/scvtf-diagnostics.s | 65 ------ llvm/test/MC/AArch64/SVE2p3/scvtf.s | 93 --------- .../MC/AArch64/SVE2p3/ucvtf-diagnostics.s | 65 ------ llvm/test/MC/AArch64/SVE2p3/ucvtf.s | 93 --------- 8 files changed, 366 insertions(+), 373 deletions(-) create mode 100644 llvm/test/MC/AArch64/SVE2p3/cvt-diagnostics.s rename llvm/test/MC/AArch64/SVE2p3/{fcvtz.s => cvt.s} (51%) delete mode 100644 llvm/test/MC/AArch64/SVE2p3/fcvtz-diagnostics.s delete mode 100644 llvm/test/MC/AArch64/SVE2p3/scvtf-diagnostics.s delete mode 100644 llvm/test/MC/AArch64/SVE2p3/scvtf.s delete mode 100644 llvm/test/MC/AArch64/SVE2p3/ucvtf-diagnostics.s delete mode 100644 llvm/test/MC/AArch64/SVE2p3/ucvtf.s diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 3255d8e6cbe74..19b42c7549a62 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -11302,7 +11302,7 @@ class sve_int_mla_cpa<string asm> } //===----------------------------------------------------------------------===// -// FCVTZSN +// FP to Int down-converts //===----------------------------------------------------------------------===// class sve2_fp_to_int_downcvt<string asm, ZPRRegOp ZdRC, RegisterOperand ZSrcOp, bits<2> size, bit U> : I<(outs ZdRC:$Zd), (ins ZSrcOp:$Zn), @@ -11325,7 +11325,7 @@ multiclass sve2_fp_to_int_downcvt<string asm, bit U> { } //===----------------------------------------------------------------------===// -// SCVTF +// Int to FP up-converts //===----------------------------------------------------------------------===// class sve2_int_to_fp_upcvt<string asm, ZPRRegOp ZdRC, ZPRRegOp ZnRC, bits<2> size, bits<2> U> diff --git a/llvm/test/MC/AArch64/SVE2p3/cvt-diagnostics.s b/llvm/test/MC/AArch64/SVE2p3/cvt-diagnostics.s new file mode 100644 index 0000000000000..a6227fb091aaf --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p3/cvt-diagnostics.s @@ -0,0 +1,193 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid operand for instruction + +fcvtzsn z0.b, { z0.b, z1.b } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvtzsn z0.b, { z0.b, z1.b } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtzsn z0.h, { z0.h, z1.h } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvtzsn z0.h, { z0.h, z1.h } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtzsn z0.s, { z0.s, z1.s } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvtzsn z0.s, { z0.s, z1.s } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtzsn z0.b, { z1.h, z2.h } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: fcvtzsn z0.b, { z1.h, z2.h } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +fcvtzsn z0.b, { z0.h, z1.h } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvtzsn z0.b, { z0.h, z1.h } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid operand for instruction + +fcvtzun z0.b, { z0.b, z1.b } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvtzun z0.b, { z0.b, z1.b } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtzun z0.h, { z0.h, z1.h } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvtzun z0.h, { z0.h, z1.h } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtzun z0.s, { z0.s, z1.s } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvtzun z0.s, { z0.s, z1.s } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtzun z0.b, { z1.h, z2.h } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: fcvtzun z0.b, { z1.h, z2.h } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +fcvtzun z0.b, { z0.h, z1.h } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvtzun z0.b, { z0.h, z1.h } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +scvtf z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: scvtf z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +scvtf z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: scvtf z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +scvtf z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: scvtf z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +scvtf z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: scvtf z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +scvtf z0.h, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: scvtf z0.h, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +scvtflt z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: scvtflt z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +scvtflt z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: scvtflt z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +scvtflt z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: scvtflt z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +scvtflt z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: scvtflt z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +scvtflt z0.h, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: scvtflt z0.h, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +ucvtf z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ucvtf z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ucvtf z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ucvtf z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ucvtf z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ucvtf z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ucvtf z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ucvtf z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +ucvtf z0.h, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ucvtf z0.h, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +ucvtflt z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ucvtflt z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ucvtflt z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ucvtflt z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ucvtflt z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ucvtflt z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ucvtflt z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ucvtflt z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +ucvtflt z0.h, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ucvtflt z0.h, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p3/fcvtz.s b/llvm/test/MC/AArch64/SVE2p3/cvt.s similarity index 51% rename from llvm/test/MC/AArch64/SVE2p3/fcvtz.s rename to llvm/test/MC/AArch64/SVE2p3/cvt.s index af01f348e71b1..c8ea3b31f8ce8 100644 --- a/llvm/test/MC/AArch64/SVE2p3/fcvtz.s +++ b/llvm/test/MC/AArch64/SVE2p3/cvt.s @@ -163,3 +163,174 @@ fcvtzun z31.s, { z30.d, z31.d } // CHECK-ENCODING: encoding: [0xdf,0x37,0xcd,0x65] // CHECK-ERROR: instruction requires: sme2p3 or sve2p3 // CHECK-UNKNOWN: 65cd37df <unknown> + +// ----------------------------------------------------------------------- +// Signed integer convert to floating-point (bottom, unpredicated) + +scvtf z0.h, z0.b +// CHECK-INST: scvtf z0.h, z0.b +// CHECK-ENCODING: encoding: [0x00,0x30,0x4c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654c3000 <unknown> + +scvtf z31.h, z31.b +// CHECK-INST: scvtf z31.h, z31.b +// CHECK-ENCODING: encoding: [0xff,0x33,0x4c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654c33ff <unknown> + +scvtf z0.s, z0.h +// CHECK-INST: scvtf z0.s, z0.h +// CHECK-ENCODING: encoding: [0x00,0x30,0x8c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658c3000 <unknown> + +scvtf z31.s, z31.h +// CHECK-INST: scvtf z31.s, z31.h +// CHECK-ENCODING: encoding: [0xff,0x33,0x8c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658c33ff <unknown> + +scvtf z0.d, z0.s +// CHECK-INST: scvtf z0.d, z0.s +// CHECK-ENCODING: encoding: [0x00,0x30,0xcc,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cc3000 <unknown> + +scvtf z31.d, z31.s +// CHECK-INST: scvtf z31.d, z31.s +// CHECK-ENCODING: encoding: [0xff,0x33,0xcc,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cc33ff <unknown> + +// ----------------------------------------------------------------------- +// Signed integer convert to floating-point (top, unpredicated) + +scvtflt z0.h, z0.b +// CHECK-INST: scvtflt z0.h, z0.b +// CHECK-ENCODING: encoding: [0x00,0x38,0x4c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654c3800 <unknown> + +scvtflt z31.h, z31.b +// CHECK-INST: scvtflt z31.h, z31.b +// CHECK-ENCODING: encoding: [0xff,0x3b,0x4c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654c3bff <unknown> + +scvtflt z0.s, z0.h +// CHECK-INST: scvtflt z0.s, z0.h +// CHECK-ENCODING: encoding: [0x00,0x38,0x8c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658c3800 <unknown> + +scvtflt z31.s, z31.h +// CHECK-INST: scvtflt z31.s, z31.h +// CHECK-ENCODING: encoding: [0xff,0x3b,0x8c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658c3bff <unknown> + +scvtflt z0.d, z0.s +// CHECK-INST: scvtflt z0.d, z0.s +// CHECK-ENCODING: encoding: [0x00,0x38,0xcc,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cc3800 <unknown> + +scvtflt z31.d, z31.s +// CHECK-INST: scvtflt z31.d, z31.s +// CHECK-ENCODING: encoding: [0xff,0x3b,0xcc,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cc3bff <unknown> +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p3 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p3 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p3 < %s \ +// RUN: | llvm-objdump -d --mattr=-sve2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p3 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +// ----------------------------------------------------------------------- +// Unsigned integer convert to floating-point (bottom, unpredicated) + +ucvtf z0.h, z0.b +// CHECK-INST: ucvtf z0.h, z0.b +// CHECK-ENCODING: encoding: [0x00,0x34,0x4c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654c3400 <unknown> + +ucvtf z31.h, z31.b +// CHECK-INST: ucvtf z31.h, z31.b +// CHECK-ENCODING: encoding: [0xff,0x37,0x4c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654c37ff <unknown> + +ucvtf z0.s, z0.h +// CHECK-INST: ucvtf z0.s, z0.h +// CHECK-ENCODING: encoding: [0x00,0x34,0x8c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658c3400 <unknown> + +ucvtf z31.s, z31.h +// CHECK-INST: ucvtf z31.s, z31.h +// CHECK-ENCODING: encoding: [0xff,0x37,0x8c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658c37ff <unknown> + +ucvtf z0.d, z0.s +// CHECK-INST: ucvtf z0.d, z0.s +// CHECK-ENCODING: encoding: [0x00,0x34,0xcc,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cc3400 <unknown> + +ucvtf z31.d, z31.s +// CHECK-INST: ucvtf z31.d, z31.s +// CHECK-ENCODING: encoding: [0xff,0x37,0xcc,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cc37ff <unknown> + +// ----------------------------------------------------------------------- +// Unsigned integer convert to floating-point (top, unpredicated) + +ucvtflt z0.h, z0.b +// CHECK-INST: ucvtflt z0.h, z0.b +// CHECK-ENCODING: encoding: [0x00,0x3c,0x4c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654c3c00 <unknown> + +ucvtflt z31.h, z31.b +// CHECK-INST: ucvtflt z31.h, z31.b +// CHECK-ENCODING: encoding: [0xff,0x3f,0x4c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 654c3fff <unknown> + +ucvtflt z0.s, z0.h +// CHECK-INST: ucvtflt z0.s, z0.h +// CHECK-ENCODING: encoding: [0x00,0x3c,0x8c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658c3c00 <unknown> + +ucvtflt z31.s, z31.h +// CHECK-INST: ucvtflt z31.s, z31.h +// CHECK-ENCODING: encoding: [0xff,0x3f,0x8c,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 658c3fff <unknown> + +ucvtflt z0.d, z0.s +// CHECK-INST: ucvtflt z0.d, z0.s +// CHECK-ENCODING: encoding: [0x00,0x3c,0xcc,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cc3c00 <unknown> + +ucvtflt z31.d, z31.s +// CHECK-INST: ucvtflt z31.d, z31.s +// CHECK-ENCODING: encoding: [0xff,0x3f,0xcc,0x65] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 65cc3fff <unknown> diff --git a/llvm/test/MC/AArch64/SVE2p3/fcvtz-diagnostics.s b/llvm/test/MC/AArch64/SVE2p3/fcvtz-diagnostics.s deleted file mode 100644 index bd182e8713e18..0000000000000 --- a/llvm/test/MC/AArch64/SVE2p3/fcvtz-diagnostics.s +++ /dev/null @@ -1,55 +0,0 @@ -// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 2>&1 < %s| FileCheck %s - -// --------------------------------------------------------------------------// -// Invalid operand for instruction - -fcvtzsn z0.b, { z0.b, z1.b } -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction -// CHECK-NEXT: fcvtzsn z0.b, { z0.b, z1.b } -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -fcvtzsn z0.h, { z0.h, z1.h } -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction -// CHECK-NEXT: fcvtzsn z0.h, { z0.h, z1.h } -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -fcvtzsn z0.s, { z0.s, z1.s } -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction -// CHECK-NEXT: fcvtzsn z0.s, { z0.s, z1.s } -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -// --------------------------------------------------------------------------// -// Negative tests for instructions that are incompatible with movprfx - -movprfx z0, z7 -fcvtzsn z0.b, { z0.h, z1.h } -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov -// CHECK-NEXT: fcvtzsn z0.b, { z0.h, z1.h } -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -// --------------------------------------------------------------------------// -// Invalid operand for instruction - -fcvtzun z0.b, { z0.b, z1.b } -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction -// CHECK-NEXT: fcvtzun z0.b, { z0.b, z1.b } -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -fcvtzun z0.h, { z0.h, z1.h } -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction -// CHECK-NEXT: fcvtzun z0.h, { z0.h, z1.h } -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -fcvtzun z0.s, { z0.s, z1.s } -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction -// CHECK-NEXT: fcvtzun z0.s, { z0.s, z1.s } -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -// --------------------------------------------------------------------------// -// Negative tests for instructions that are incompatible with movprfx - -movprfx z0, z7 -fcvtzun z0.b, { z0.h, z1.h } -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov -// CHECK-NEXT: fcvtzun z0.b, { z0.h, z1.h } -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p3/scvtf-diagnostics.s b/llvm/test/MC/AArch64/SVE2p3/scvtf-diagnostics.s deleted file mode 100644 index add25d926a55d..0000000000000 --- a/llvm/test/MC/AArch64/SVE2p3/scvtf-diagnostics.s +++ /dev/null @@ -1,65 +0,0 @@ -// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 2>&1 < %s| FileCheck %s - -// --------------------------------------------------------------------------// -// Invalid element width - -scvtf z0.b, z0.b -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width -// CHECK-NEXT: scvtf z0.b, z0.b -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -scvtf z0.h, z0.h -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width -// CHECK-NEXT: scvtf z0.h, z0.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -scvtf z0.s, z0.s -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width -// CHECK-NEXT: scvtf z0.s, z0.s -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -scvtf z0.d, z0.d -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width -// CHECK-NEXT: scvtf z0.d, z0.d -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -// --------------------------------------------------------------------------// -// Negative tests for instructions that are incompatible with movprfx - -movprfx z0, z7 -scvtf z0.h, z0.b -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov -// CHECK-NEXT: scvtf z0.h, z0.b -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -// --------------------------------------------------------------------------// -// Invalid element width - -scvtflt z0.b, z0.b -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width -// CHECK-NEXT: scvtflt z0.b, z0.b -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -scvtflt z0.h, z0.h -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width -// CHECK-NEXT: scvtflt z0.h, z0.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -scvtflt z0.s, z0.s -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width -// CHECK-NEXT: scvtflt z0.s, z0.s -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -scvtflt z0.d, z0.d -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width -// CHECK-NEXT: scvtflt z0.d, z0.d -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -// --------------------------------------------------------------------------// -// Negative tests for instructions that are incompatible with movprfx - -movprfx z0, z7 -scvtflt z0.h, z0.b -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov -// CHECK-NEXT: scvtflt z0.h, z0.b -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p3/scvtf.s b/llvm/test/MC/AArch64/SVE2p3/scvtf.s deleted file mode 100644 index 2d6b71355c1f3..0000000000000 --- a/llvm/test/MC/AArch64/SVE2p3/scvtf.s +++ /dev/null @@ -1,93 +0,0 @@ -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 < %s \ -// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p3 < %s \ -// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST -// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ -// RUN: | FileCheck %s --check-prefix=CHECK-ERROR -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p3 < %s \ -// RUN: | llvm-objdump -d --mattr=+sve2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p3 < %s \ -// RUN: | llvm-objdump -d --mattr=-sve2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN -// Disassemble encoding and check the re-encoding (-show-encoding) matches. -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 < %s \ -// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ -// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p3 -disassemble -show-encoding \ -// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST - -// ----------------------------------------------------------------------- -// Signed integer convert to floating-point (bottom, unpredicated) - -scvtf z0.h, z0.b -// CHECK-INST: scvtf z0.h, z0.b -// CHECK-ENCODING: encoding: [0x00,0x30,0x4c,0x65] -// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 -// CHECK-UNKNOWN: 654c3000 <unknown> - -scvtf z31.h, z31.b -// CHECK-INST: scvtf z31.h, z31.b -// CHECK-ENCODING: encoding: [0xff,0x33,0x4c,0x65] -// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 -// CHECK-UNKNOWN: 654c33ff <unknown> - -scvtf z0.s, z0.h -// CHECK-INST: scvtf z0.s, z0.h -// CHECK-ENCODING: encoding: [0x00,0x30,0x8c,0x65] -// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 -// CHECK-UNKNOWN: 658c3000 <unknown> - -scvtf z31.s, z31.h -// CHECK-INST: scvtf z31.s, z31.h -// CHECK-ENCODING: encoding: [0xff,0x33,0x8c,0x65] -// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 -// CHECK-UNKNOWN: 658c33ff <unknown> - -scvtf z0.d, z0.s -// CHECK-INST: scvtf z0.d, z0.s -// CHECK-ENCODING: encoding: [0x00,0x30,0xcc,0x65] -// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 -// CHECK-UNKNOWN: 65cc3000 <unknown> - -scvtf z31.d, z31.s -// CHECK-INST: scvtf z31.d, z31.s -// CHECK-ENCODING: encoding: [0xff,0x33,0xcc,0x65] -// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 -// CHECK-UNKNOWN: 65cc33ff <unknown> - -// ----------------------------------------------------------------------- -// Signed integer convert to floating-point (top, unpredicated) - -scvtflt z0.h, z0.b -// CHECK-INST: scvtflt z0.h, z0.b -// CHECK-ENCODING: encoding: [0x00,0x38,0x4c,0x65] -// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 -// CHECK-UNKNOWN: 654c3800 <unknown> - -scvtflt z31.h, z31.b -// CHECK-INST: scvtflt z31.h, z31.b -// CHECK-ENCODING: encoding: [0xff,0x3b,0x4c,0x65] -// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 -// CHECK-UNKNOWN: 654c3bff <unknown> - -scvtflt z0.s, z0.h -// CHECK-INST: scvtflt z0.s, z0.h -// CHECK-ENCODING: encoding: [0x00,0x38,0x8c,0x65] -// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 -// CHECK-UNKNOWN: 658c3800 <unknown> - -scvtflt z31.s, z31.h -// CHECK-INST: scvtflt z31.s, z31.h -// CHECK-ENCODING: encoding: [0xff,0x3b,0x8c,0x65] -// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 -// CHECK-UNKNOWN: 658c3bff <unknown> - -scvtflt z0.d, z0.s -// CHECK-INST: scvtflt z0.d, z0.s -// CHECK-ENCODING: encoding: [0x00,0x38,0xcc,0x65] -// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 -// CHECK-UNKNOWN: 65cc3800 <unknown> - -scvtflt z31.d, z31.s -// CHECK-INST: scvtflt z31.d, z31.s -// CHECK-ENCODING: encoding: [0xff,0x3b,0xcc,0x65] -// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 -// CHECK-UNKNOWN: 65cc3bff <unknown> diff --git a/llvm/test/MC/AArch64/SVE2p3/ucvtf-diagnostics.s b/llvm/test/MC/AArch64/SVE2p3/ucvtf-diagnostics.s deleted file mode 100644 index 49c798f9298dd..0000000000000 --- a/llvm/test/MC/AArch64/SVE2p3/ucvtf-diagnostics.s +++ /dev/null @@ -1,65 +0,0 @@ -// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 2>&1 < %s| FileCheck %s - -// --------------------------------------------------------------------------// -// Invalid element width - -ucvtf z0.b, z0.b -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width -// CHECK-NEXT: ucvtf z0.b, z0.b -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -ucvtf z0.h, z0.h -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width -// CHECK-NEXT: ucvtf z0.h, z0.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -ucvtf z0.s, z0.s -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width -// CHECK-NEXT: ucvtf z0.s, z0.s -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -ucvtf z0.d, z0.d -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width -// CHECK-NEXT: ucvtf z0.d, z0.d -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -// --------------------------------------------------------------------------// -// Negative tests for instructions that are incompatible with movprfx - -movprfx z0, z7 -ucvtf z0.h, z0.b -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov -// CHECK-NEXT: ucvtf z0.h, z0.b -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -// --------------------------------------------------------------------------// -// Invalid element width - -ucvtflt z0.b, z0.b -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width -// CHECK-NEXT: ucvtflt z0.b, z0.b -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -ucvtflt z0.h, z0.h -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width -// CHECK-NEXT: ucvtflt z0.h, z0.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -ucvtflt z0.s, z0.s -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width -// CHECK-NEXT: ucvtflt z0.s, z0.s -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -ucvtflt z0.d, z0.d -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width -// CHECK-NEXT: ucvtflt z0.d, z0.d -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -// --------------------------------------------------------------------------// -// Negative tests for instructions that are incompatible with movprfx - -movprfx z0, z7 -ucvtflt z0.h, z0.b -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov -// CHECK-NEXT: ucvtflt z0.h, z0.b -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p3/ucvtf.s b/llvm/test/MC/AArch64/SVE2p3/ucvtf.s deleted file mode 100644 index a34c58066433f..0000000000000 --- a/llvm/test/MC/AArch64/SVE2p3/ucvtf.s +++ /dev/null @@ -1,93 +0,0 @@ -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 < %s \ -// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p3 < %s \ -// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST -// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ -// RUN: | FileCheck %s --check-prefix=CHECK-ERROR -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p3 < %s \ -// RUN: | llvm-objdump -d --mattr=+sve2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p3 < %s \ -// RUN: | llvm-objdump -d --mattr=-sve2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN -// Disassemble encoding and check the re-encoding (-show-encoding) matches. -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 < %s \ -// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ -// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p3 -disassemble -show-encoding \ -// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST - -// ----------------------------------------------------------------------- -// Unsigned integer convert to floating-point (bottom, unpredicated) - -ucvtf z0.h, z0.b -// CHECK-INST: ucvtf z0.h, z0.b -// CHECK-ENCODING: encoding: [0x00,0x34,0x4c,0x65] -// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 -// CHECK-UNKNOWN: 654c3400 <unknown> - -ucvtf z31.h, z31.b -// CHECK-INST: ucvtf z31.h, z31.b -// CHECK-ENCODING: encoding: [0xff,0x37,0x4c,0x65] -// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 -// CHECK-UNKNOWN: 654c37ff <unknown> - -ucvtf z0.s, z0.h -// CHECK-INST: ucvtf z0.s, z0.h -// CHECK-ENCODING: encoding: [0x00,0x34,0x8c,0x65] -// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 -// CHECK-UNKNOWN: 658c3400 <unknown> - -ucvtf z31.s, z31.h -// CHECK-INST: ucvtf z31.s, z31.h -// CHECK-ENCODING: encoding: [0xff,0x37,0x8c,0x65] -// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 -// CHECK-UNKNOWN: 658c37ff <unknown> - -ucvtf z0.d, z0.s -// CHECK-INST: ucvtf z0.d, z0.s -// CHECK-ENCODING: encoding: [0x00,0x34,0xcc,0x65] -// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 -// CHECK-UNKNOWN: 65cc3400 <unknown> - -ucvtf z31.d, z31.s -// CHECK-INST: ucvtf z31.d, z31.s -// CHECK-ENCODING: encoding: [0xff,0x37,0xcc,0x65] -// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 -// CHECK-UNKNOWN: 65cc37ff <unknown> - -// ----------------------------------------------------------------------- -// Unsigned integer convert to floating-point (top, unpredicated) - -ucvtflt z0.h, z0.b -// CHECK-INST: ucvtflt z0.h, z0.b -// CHECK-ENCODING: encoding: [0x00,0x3c,0x4c,0x65] -// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 -// CHECK-UNKNOWN: 654c3c00 <unknown> - -ucvtflt z31.h, z31.b -// CHECK-INST: ucvtflt z31.h, z31.b -// CHECK-ENCODING: encoding: [0xff,0x3f,0x4c,0x65] -// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 -// CHECK-UNKNOWN: 654c3fff <unknown> - -ucvtflt z0.s, z0.h -// CHECK-INST: ucvtflt z0.s, z0.h -// CHECK-ENCODING: encoding: [0x00,0x3c,0x8c,0x65] -// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 -// CHECK-UNKNOWN: 658c3c00 <unknown> - -ucvtflt z31.s, z31.h -// CHECK-INST: ucvtflt z31.s, z31.h -// CHECK-ENCODING: encoding: [0xff,0x3f,0x8c,0x65] -// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 -// CHECK-UNKNOWN: 658c3fff <unknown> - -ucvtflt z0.d, z0.s -// CHECK-INST: ucvtflt z0.d, z0.s -// CHECK-ENCODING: encoding: [0x00,0x3c,0xcc,0x65] -// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 -// CHECK-UNKNOWN: 65cc3c00 <unknown> - -ucvtflt z31.d, z31.s -// CHECK-INST: ucvtflt z31.d, z31.s -// CHECK-ENCODING: encoding: [0xff,0x3f,0xcc,0x65] -// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 -// CHECK-UNKNOWN: 65cc3fff <unknown> _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
