https://github.com/jthackray updated https://github.com/llvm/llvm-project/pull/163159
>From 9032547897ff4b143b747338d8ecd628f6be8c60 Mon Sep 17 00:00:00 2001 From: Jonathan Thackray <[email protected]> Date: Wed, 20 Aug 2025 20:26:40 +0100 Subject: [PATCH 1/3] [AArch64][llvm] Armv9.7-A: Add support for GICv5 (FEAT_GCIE) Add new instruction and system registers that are specified in the Generic Interrupt Controller Architecture v5 (GICv5) standard, announced here: * https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/introducing-gicv5 and documented here: * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions * https://developer.arm.com/documentation/ddi0602/2025-09/ Co-authored-by: Jack Styles <[email protected]> --- clang/test/Driver/aarch64-v97a.c | 4 + .../print-supported-extensions-aarch64.c | 1 + llvm/lib/Target/AArch64/AArch64Features.td | 3 + llvm/lib/Target/AArch64/AArch64InstrInfo.td | 2 + .../Target/AArch64/AArch64SystemOperands.td | 208 ++++ .../AArch64/AsmParser/AArch64AsmParser.cpp | 85 +- .../MCTargetDesc/AArch64InstPrinter.cpp | 79 +- .../AArch64/MCTargetDesc/AArch64InstPrinter.h | 2 + .../Target/AArch64/Utils/AArch64BaseInfo.cpp | 21 + .../Target/AArch64/Utils/AArch64BaseInfo.h | 24 + llvm/test/MC/AArch64/armv9.7a-gcie.s | 985 ++++++++++++++++++ .../TargetParser/TargetParserTest.cpp | 3 + 12 files changed, 1411 insertions(+), 6 deletions(-) create mode 100644 llvm/test/MC/AArch64/armv9.7a-gcie.s diff --git a/clang/test/Driver/aarch64-v97a.c b/clang/test/Driver/aarch64-v97a.c index 5f2631701ba4c..008f79e11e18c 100644 --- a/clang/test/Driver/aarch64-v97a.c +++ b/clang/test/Driver/aarch64-v97a.c @@ -37,3 +37,7 @@ // RUN: %clang -target aarch64 -march=armv9.7a+mtetc -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MTETC %s // RUN: %clang -target aarch64 -march=armv9.7-a+mtetc -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MTETC %s // V97A-MTETC: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+mtetc" + +// RUN: %clang -target aarch64 -march=armv9.7a+gcie -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-GCIE %s +// RUN: %clang -target aarch64 -march=armv9.7-a+gcie -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-GCIE %s +// VFAT-GCIE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+gcie" diff --git a/clang/test/Driver/print-supported-extensions-aarch64.c b/clang/test/Driver/print-supported-extensions-aarch64.c index 05ecc0dd8ec89..1516ed8b30912 100644 --- a/clang/test/Driver/print-supported-extensions-aarch64.c +++ b/clang/test/Driver/print-supported-extensions-aarch64.c @@ -32,6 +32,7 @@ // CHECK-NEXT: fp8fma FEAT_FP8FMA Enable Armv9.5-A FP8 multiply-add instructions // CHECK-NEXT: fprcvt FEAT_FPRCVT Enable Armv9.6-A base convert instructions for SIMD&FP scalar register operands of different input and output sizes // CHECK-NEXT: fp16 FEAT_FP16 Enable half-precision floating-point data processing +// CHECK-NEXT: gcie FEAT_GCIE Enable Armv9.7-A GICv5 (Generic Interrupt Controller) CPU Interface Extension // CHECK-NEXT: gcs FEAT_GCS Enable Armv9.4-A Guarded Call Stack Extension // CHECK-NEXT: hbc FEAT_HBC Enable Armv8.8-A Hinted Conditional Branches Extension // CHECK-NEXT: i8mm FEAT_I8MM Enable Matrix Multiply Int8 Extension diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td index d0b7ed34d0309..0b117a22f5721 100644 --- a/llvm/lib/Target/AArch64/AArch64Features.td +++ b/llvm/lib/Target/AArch64/AArch64Features.td @@ -604,6 +604,9 @@ def FeatureMPAMv2: ExtensionWithMArch<"mpamv2", "MPAMv2", "FEAT_MPAMv2", def FeatureMTETC: ExtensionWithMArch<"mtetc", "MTETC", "FEAT_MTETC", "Enable Virtual Memory Tagging Extension">; +def FeatureGCIE: ExtensionWithMArch<"gcie", "GCIE", "FEAT_GCIE", + "Enable Armv9.7-A GICv5 (Generic Interrupt Controller) CPU Interface Extension", [FeatureNMI]>; + //===----------------------------------------------------------------------===// // Other Features //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 390f91a89af9f..359692b43e1d8 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -406,6 +406,8 @@ def HasMPAMv2 : Predicate<"Subtarget->hasMPAMv2()">, AssemblerPredicateWithAll<(all_of FeatureMPAMv2), "mpamv2">; def HasMTETC : Predicate<"Subtarget->hasMTETC()">, AssemblerPredicateWithAll<(all_of FeatureMTETC), "mtetc">; +def HasGCIE : Predicate<"Subtarget->hasGCIE()">, + AssemblerPredicateWithAll<(all_of FeatureGCIE), "gcie">; def IsLE : Predicate<"Subtarget->isLittleEndian()">; def IsBE : Predicate<"!Subtarget->isLittleEndian()">; def IsWindows : Predicate<"Subtarget->isTargetWindows()">; diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td index db560f0786a3e..33bbf1a33ba2a 100644 --- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -2493,3 +2493,211 @@ def : MLBI<"ALLE1", 0b100, 0b0111, 0b0000, 0b100, 0>; def : MLBI<"VMALLE1", 0b100, 0b0111, 0b0000, 0b101, 0>; def : MLBI<"VPIDE1", 0b100, 0b0111, 0b0000, 0b110, 1>; def : MLBI<"VPMGE1", 0b100, 0b0111, 0b0000, 0b111, 1>; + + +// v9.7-A GICv5 (FEAT_GCIE) +// CPU Interface Registers +// Op0 Op1 CRn CRm Op2 +def : RWSysReg<"ICC_APR_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b000>; +def : RWSysReg<"ICC_APR_EL3", 0b11, 0b110, 0b1100, 0b1000, 0b000>; +def : RWSysReg<"ICC_CR0_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b001>; +def : RWSysReg<"ICC_CR0_EL3", 0b11, 0b110, 0b1100, 0b1001, 0b000>; +def : ROSysReg<"ICC_DOMHPPIR_EL3", 0b11, 0b110, 0b1100, 0b1000, 0b010>; +def : ROSysReg<"ICC_HAPR_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b011>; +def : ROSysReg<"ICC_HPPIR_EL1", 0b11, 0b000, 0b1100, 0b1010, 0b011>; +def : ROSysReg<"ICC_HPPIR_EL3", 0b11, 0b110, 0b1100, 0b1001, 0b001>; +def : ROSysReg<"ICC_IAFFIDR_EL1", 0b11, 0b000, 0b1100, 0b1010, 0b101>; +def : RWSysReg<"ICC_ICSR_EL1", 0b11, 0b000, 0b1100, 0b1010, 0b100>; +def : ROSysReg<"ICC_IDR0_EL1", 0b11, 0b000, 0b1100, 0b1010, 0b010>; +def : RWSysReg<"ICC_PCR_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b010>; +def : RWSysReg<"ICC_PCR_EL3", 0b11, 0b110, 0b1100, 0b1000, 0b001>; + +// Virtual CPU Interface Registers +// Op0 Op1 CRn CRm Op2 +def : RWSysReg<"ICV_APR_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b000>; +def : RWSysReg<"ICV_CR0_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b001>; +def : RWSysReg<"ICV_HAPR_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b011>; +def : RWSysReg<"ICV_HPPIR_EL1", 0b11, 0b000, 0b1100, 0b1010, 0b011>; +def : RWSysReg<"ICV_PCR_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b010>; + +// PPI Registers +foreach n=0-1 in { + defvar nb = !cast<bit>(n); +// Op0 Op1 CRn CRm Op2 + def : RWSysReg<"ICC_PPI_CACTIVER"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b00,nb}>; + def : RWSysReg<"ICC_PPI_CPENDR"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b10,nb}>; + def : RWSysReg<"ICC_PPI_ENABLER"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1010, {0b11,nb}>; + def : RWSysReg<"ICC_PPI_SACTIVER"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b01,nb}>; + def : RWSysReg<"ICC_PPI_SPENDR"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b11,nb}>; + def : ROSysReg<"ICC_PPI_HMR"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1010, {0b00,nb}>; +} + +foreach n=0-3 in { + defvar nb = !cast<bits<2>>(n); +// Op0 Op1 CRn CRm Op2 + def : RWSysReg<"ICC_PPI_DOMAINR"#n#"_EL3", 0b11, 0b110, 0b1100, 0b1000, {0b1,nb{1-0}}>; + +} + +foreach n=0-15 in{ + defvar nb = !cast<bits<4>>(n); +// Op0 Op1 CRn CRm Op2 + def : RWSysReg<"ICC_PPI_PRIORITYR"#n#"_EL1", 0b11, 0b000, 0b1100, {0b111,nb{3}}, nb{2-0}>; +} + +// Virtual PPI Registers +foreach n=0-1 in { + defvar nb = !cast<bit>(n); +// Op0 Op1 CRn CRm Op2 + def : RWSysReg<"ICV_PPI_CACTIVER"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b00,nb}>; + def : RWSysReg<"ICV_PPI_CPENDR"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b10,nb}>; + def : RWSysReg<"ICV_PPI_ENABLER"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1010, {0b11,nb}>; + def : RWSysReg<"ICV_PPI_SACTIVER"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b01,nb}>; + def : RWSysReg<"ICV_PPI_SPENDR"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b11,nb}>; + def : RWSysReg<"ICV_PPI_HMR"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1010, {0b00,nb}>; +} + +foreach n=0-15 in { + defvar nb = !cast<bits<4>>(n); +// Op0 Op1 CRn CRm Op2 + def : RWSysReg<"ICV_PPI_PRIORITYR"#n#"_EL1", 0b11, 0b000, 0b1100, {0b111,nb{3}}, nb{2-0}>; +} + +// Hypervisor Control Registers +// Op0 Op1 CRn CRm Op2 +def : RWSysReg<"ICH_APR_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b100>; +def : RWSysReg<"ICH_CONTEXTR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b110>; +def : RWSysReg<"ICH_HFGITR_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b111>; +def : RWSysReg<"ICH_HFGRTR_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b100>; +def : RWSysReg<"ICH_HFGWTR_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b110>; +def : ROSysReg<"ICH_HPPIR_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b101>; +def : RWSysReg<"ICH_VCTLR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b100>; + +foreach n=0-1 in { + defvar nb = !cast<bit>(n); +// Op0 Op1 CRn CRm Op2 +def : RWSysReg<"ICH_PPI_ACTIVER"#n#"_EL2", 0b11, 0b100, 0b1100, 0b1010, {0b11,nb}>; +def : RWSysReg<"ICH_PPI_DVIR"#n#"_EL2", 0b11, 0b100, 0b1100, 0b1010, {0b00,nb}>; +def : RWSysReg<"ICH_PPI_ENABLER"#n#"_EL2", 0b11, 0b100, 0b1100, 0b1010, {0b01,nb}>; +def : RWSysReg<"ICH_PPI_PENDR"#n#"_EL2", 0b11, 0b100, 0b1100, 0b1010, {0b10,nb}>; +} + +foreach n=0-15 in { + defvar nb = !cast<bits<4>>(n); +// Op0 Op1 CRn CRm Op2 + def : RWSysReg<"ICH_PPI_PRIORITYR"#n#"_EL2", 0b11, 0b100, 0b1100, {0b111,nb{3}}, nb{2-0}>; +} + +//===----------------------------------------------------------------------===// +// GICv5 instruction options. +//===----------------------------------------------------------------------===// + +// GIC +class GIC<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2, bit needsreg> { + string Name = name; + bits<14> Encoding; + let Encoding{13-11} = op1; + let Encoding{10-7} = crn; + let Encoding{6-3} = crm; + let Encoding{2-0} = op2; + bit NeedsReg = needsreg; + string RequiresStr = [{ {AArch64::FeatureGCIE} }]; +} + +// GSB +class GSB<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2> { + string Name = name; + bits<14> Encoding; + let Encoding{13-11} = op1; + let Encoding{10-7} = crn; + let Encoding{6-3} = crm; + let Encoding{2-0} = op2; + string RequiresStr = [{ {AArch64::FeatureGCIE} }]; +} + +// GICR +class GICR<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2, bit needsreg> { + string Name = name; + bits<14> Encoding; + let Encoding{13-11} = op1; + let Encoding{10-7} = crn; + let Encoding{6-3} = crm; + let Encoding{2-0} = op2; + bit NeedsReg = needsreg; + string RequiresStr = [{ {AArch64::FeatureGCIE} }]; +} + +def GICTable : GenericTable { + let FilterClass = "GIC"; + let CppTypeName = "GIC"; + let Fields = ["Name", "Encoding", "NeedsReg", "RequiresStr"]; + + let PrimaryKey = ["Encoding"]; + let PrimaryKeyName = "lookupGICByEncoding"; +} + +def GSBTable : GenericTable { + let FilterClass = "GSB"; + let CppTypeName = "GSB"; + let Fields = ["Name", "Encoding", "RequiresStr"]; + + let PrimaryKey = ["Encoding"]; + let PrimaryKeyName = "lookupGSBByEncoding"; +} + +def GICRTable : GenericTable { + let FilterClass = "GICR"; + let CppTypeName = "GICR"; + let Fields = ["Name", "Encoding", "NeedsReg", "RequiresStr"]; + + let PrimaryKey = ["Encoding"]; + let PrimaryKeyName = "lookupGICRByEncoding"; +} + +def lookupGICByName : SearchIndex { + let Table = GICTable; + let Key = ["Name"]; +} + +def lookupGSBByName : SearchIndex { + let Table = GSBTable; + let Key = ["Name"]; +} + +def lookupGICRByName : SearchIndex { + let Table = GICRTable; + let Key = ["Name"]; +} + +// Op1 CRn CRm Op2 +def : GSB<"sys", 0b000, 0b1100, 0b0000, 0b000>; +def : GSB<"ack", 0b000, 0b1100, 0b0000, 0b001>; + +// Op1 CRn CRm Op2 needsReg +def : GIC<"cdaff", 0b000, 0b1100, 0b0001, 0b011, 1>; +def : GIC<"cddi", 0b000, 0b1100, 0b0010, 0b000, 1>; +def : GIC<"cddis", 0b000, 0b1100, 0b0001, 0b000, 1>; +def : GIC<"cden", 0b000, 0b1100, 0b0001, 0b001, 1>; +def : GIC<"cdeoi", 0b000, 0b1100, 0b0001, 0b111, 1>; +def : GIC<"cdhm", 0b000, 0b1100, 0b0010, 0b001, 1>; +def : GIC<"cdpend", 0b000, 0b1100, 0b0001, 0b100, 1>; +def : GIC<"cdpri", 0b000, 0b1100, 0b0001, 0b010, 1>; +def : GIC<"cdrcfg", 0b000, 0b1100, 0b0001, 0b101, 1>; +def : GICR<"cdia", 0b000, 0b1100, 0b0011, 0b000, 1>; +def : GICR<"cdnmia", 0b000, 0b1100, 0b0011, 0b001, 1>; +def : GIC<"vdaff", 0b100, 0b1100, 0b0001, 0b011, 1>; +def : GIC<"vddi", 0b100, 0b1100, 0b0010, 0b000, 1>; +def : GIC<"vddis", 0b100, 0b1100, 0b0001, 0b000, 1>; +def : GIC<"vden", 0b100, 0b1100, 0b0001, 0b001, 1>; +def : GIC<"vdhm", 0b100, 0b1100, 0b0010, 0b001, 1>; +def : GIC<"vdpend", 0b100, 0b1100, 0b0001, 0b100, 1>; +def : GIC<"vdpri", 0b100, 0b1100, 0b0001, 0b010, 1>; +def : GIC<"vdrcfg", 0b100, 0b1100, 0b0001, 0b101, 1>; +def : GIC<"ldaff", 0b110, 0b1100, 0b0001, 0b011, 1>; +def : GIC<"lddi", 0b110, 0b1100, 0b0010, 0b000, 1>; +def : GIC<"lddis", 0b110, 0b1100, 0b0001, 0b000, 1>; +def : GIC<"lden", 0b110, 0b1100, 0b0001, 0b001, 1>; +def : GIC<"ldhm", 0b110, 0b1100, 0b0010, 0b001, 1>; +def : GIC<"ldpend", 0b110, 0b1100, 0b0001, 0b100, 1>; +def : GIC<"ldpri", 0b110, 0b1100, 0b0001, 0b010, 1>; +def : GIC<"ldrcfg", 0b110, 0b1100, 0b0001, 0b101, 1>; diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index e8e2f3c2ecd7e..2ff2d60c991d4 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -159,6 +159,7 @@ class AArch64AsmParser : public MCTargetAsmParser { SMLoc getLoc() const { return getParser().getTok().getLoc(); } bool parseSysAlias(StringRef Name, SMLoc NameLoc, OperandVector &Operands); + bool parseSyslAlias(StringRef Name, SMLoc NameLoc, OperandVector &Operands); bool parseSyspAlias(StringRef Name, SMLoc NameLoc, OperandVector &Operands); void createSysAlias(uint16_t Encoding, OperandVector &Operands, SMLoc S); AArch64CC::CondCode parseCondCodeString(StringRef Cond, @@ -3888,6 +3889,7 @@ static const struct Extension { {"tlbid", {AArch64::FeatureTLBID}}, {"mpamv2", {AArch64::FeatureMPAMv2}}, {"mtetc", {AArch64::FeatureMTETC}}, + {"gcie", {AArch64::FeatureGCIE}}, }; static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) { @@ -3960,7 +3962,7 @@ void AArch64AsmParser::createSysAlias(uint16_t Encoding, OperandVector &Operands AArch64Operand::CreateImm(Expr, S, getLoc(), getContext())); } -/// parseSysAlias - The IC, DC, AT, TLBI, and MLBI instructions +/// parseSysAlias - The IC, DC, AT, TLBI, MLBI and GIC{R} and GSB instructions /// are simple aliases for the SYS instruction. Parse them specially so that /// we create a SYS MCInst. bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc, @@ -4035,6 +4037,28 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc, } ExpectRegister = MLBI->NeedsReg; createSysAlias(MLBI->Encoding, Operands, S); + } else if (Mnemonic == "gic") { + const AArch64GIC::GIC *GIC = AArch64GIC::lookupGICByName(Op); + if (!GIC) + return TokError("invalid operand for GIC instruction"); + else if (!GIC->haveFeatures(getSTI().getFeatureBits())) { + std::string Str("GIC " + std::string(GIC->Name) + " requires: "); + setRequiredFeatureString(GIC->getRequiredFeatures(), Str); + return TokError(Str); + } + ExpectRegister = GIC->NeedsReg; + createSysAlias(GIC->Encoding, Operands, S); + } else if (Mnemonic == "gsb") { + const AArch64GSB::GSB *GSB = AArch64GSB::lookupGSBByName(Op); + if (!GSB) + return TokError("invalid operand for GSB instruction"); + else if (!GSB->haveFeatures(getSTI().getFeatureBits())) { + std::string Str("GSB " + std::string(GSB->Name) + " requires: "); + setRequiredFeatureString(GSB->getRequiredFeatures(), Str); + return TokError(Str); + } + ExpectRegister = false; + createSysAlias(GSB->Encoding, Operands, S); } else if (Mnemonic == "cfp" || Mnemonic == "dvp" || Mnemonic == "cpp" || Mnemonic == "cosp") { @@ -4086,6 +4110,55 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc, return false; } +/// parseSyslAlias - The GICR instructions are simple aliases for +/// the SYSL instruction. Parse them specially so that we create a +/// SYS MCInst. +bool AArch64AsmParser::parseSyslAlias(StringRef Name, SMLoc NameLoc, + OperandVector &Operands) { + + Mnemonic = Name; + Operands.push_back( + AArch64Operand::CreateToken("sysl", NameLoc, getContext())); + + // Now expect two operands (identifier + register) + SMLoc startLoc = getLoc(); + const AsmToken ®Tok = getTok(); + StringRef reg = regTok.getString(); + unsigned RegNum = matchRegisterNameAlias(reg.lower(), RegKind::Scalar); + if (!RegNum) + return TokError("expected register operand"); + + Operands.push_back(AArch64Operand::CreateReg( + RegNum, RegKind::Scalar, startLoc, getLoc(), getContext(), EqualsReg)); + + Lex(); // Eat token + if (parseToken(AsmToken::Comma)) + return true; + + // Check for identifier + const AsmToken &operandTok = getTok(); + StringRef Op = operandTok.getString(); + SMLoc S2 = operandTok.getLoc(); + Lex(); // Eat token + + if (Mnemonic == "gicr") { + const AArch64GICR::GICR *GICR = AArch64GICR::lookupGICRByName(Op); + if (!GICR) + return Error(S2, "invalid operand for GICR instruction"); + else if (!GICR->haveFeatures(getSTI().getFeatureBits())) { + std::string Str("GICR " + std::string(GICR->Name) + " requires: "); + setRequiredFeatureString(GICR->getRequiredFeatures(), Str); + return Error(S2, Str); + } + createSysAlias(GICR->Encoding, Operands, S2); + } + + if (parseToken(AsmToken::EndOfStatement, "unexpected token in argument list")) + return true; + + return false; +} + /// parseSyspAlias - The TLBIP instructions are simple aliases for /// the SYSP instruction. Parse them specially so that we create a SYSP MCInst. bool AArch64AsmParser::parseSyspAlias(StringRef Name, SMLoc NameLoc, @@ -5353,13 +5426,17 @@ bool AArch64AsmParser::parseInstruction(ParseInstructionInfo &Info, size_t Start = 0, Next = Name.find('.'); StringRef Head = Name.slice(Start, Next); - // IC, DC, AT, TLBI, MLBI and Prediction invalidation instructions are aliases - // for the SYS instruction. + // IC, DC, AT, TLBI, MLBI, GIC{R}, GSB and Prediction invalidation + // instructions are aliases for the SYS instruction. if (Head == "ic" || Head == "dc" || Head == "at" || Head == "tlbi" || Head == "cfp" || Head == "dvp" || Head == "cpp" || Head == "cosp" || - Head == "mlbi") + Head == "mlbi" || Head == "gic" || Head == "gsb") return parseSysAlias(Head, NameLoc, Operands); + // GICR instructions are aliases for the SYSL instruction. + if (Head == "gicr") + return parseSyslAlias(Head, NameLoc, Operands); + // TLBIP instructions are aliases for the SYSP instruction. if (Head == "tlbip") return parseSyspAlias(Head, NameLoc, Operands); diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp index 9765c7189dcab..358098402bcce 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp @@ -84,6 +84,12 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address, return; } + if (Opcode == AArch64::SYSLxt) + if (printSyslAlias(MI, STI, O)) { + printAnnotation(O, Annot); + return; + } + if (Opcode == AArch64::SYSPxt || Opcode == AArch64::SYSPxt_XZR) if (printSyspAlias(MI, STI, O)) { printAnnotation(O, Annot); @@ -1021,8 +1027,27 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI, OptionalReg = TLBI->OptionalReg; Ins = "tlbi\t"; Name = std::string(TLBI->Name); - } - else + } else if (CnVal == 12) { + if (CmVal != 0) { + // GIC aliases + const AArch64GIC::GIC *GIC = AArch64GIC::lookupGICByEncoding(Encoding); + if (!GIC || !GIC->haveFeatures(STI.getFeatureBits())) + return false; + + NeedsReg = GIC->NeedsReg; + Ins = "gic\t"; + Name = std::string(GIC->Name); + } else { + // GSB aliases + const AArch64GSB::GSB *GSB = AArch64GSB::lookupGSBByEncoding(Encoding); + if (!GSB || !GSB->haveFeatures(STI.getFeatureBits())) + return false; + + NeedsReg = false; + Ins = "gsb\t"; + Name = std::string(GSB->Name); + } + } else return false; StringRef Reg = getRegisterName(MI->getOperand(4).getReg()); @@ -1047,6 +1072,56 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI, return true; } +bool AArch64InstPrinter::printSyslAlias(const MCInst *MI, + const MCSubtargetInfo &STI, + raw_ostream &O) { +#ifndef NDEBUG + unsigned Opcode = MI->getOpcode(); + assert(Opcode == AArch64::SYSLxt && "Invalid opcode for SYSL alias!"); +#endif + + StringRef Reg = getRegisterName(MI->getOperand(0).getReg()); + const MCOperand &Op1 = MI->getOperand(1); + const MCOperand &Cn = MI->getOperand(2); + const MCOperand &Cm = MI->getOperand(3); + const MCOperand &Op2 = MI->getOperand(4); + + unsigned Op1Val = Op1.getImm(); + unsigned CnVal = Cn.getImm(); + unsigned CmVal = Cm.getImm(); + unsigned Op2Val = Op2.getImm(); + + uint16_t Encoding = Op2Val; + Encoding |= CmVal << 3; + Encoding |= CnVal << 7; + Encoding |= Op1Val << 11; + + std::string Ins; + std::string Name; + + if (CnVal == 12) { + if (CmVal == 3) { + // GICR aliases + const AArch64GICR::GICR *GICR = + AArch64GICR::lookupGICRByEncoding(Encoding); + if (!GICR || !GICR->haveFeatures(STI.getFeatureBits())) + return false; + + Ins = "gicr"; + Name = std::string(GICR->Name); + } else + return false; + } else + return false; + + std::string Str; + llvm::transform(Name, Name.begin(), ::tolower); + + O << '\t' << Ins << '\t' << Reg.str() << ", " << Name; + + return true; +} + bool AArch64InstPrinter::printSyspAlias(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O) { diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h index 2bdf40a3cfc5e..307402d920d32 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h @@ -52,6 +52,8 @@ class AArch64InstPrinter : public MCInstPrinter { protected: bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O); + bool printSyslAlias(const MCInst *MI, const MCSubtargetInfo &STI, + raw_ostream &O); bool printSyspAlias(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O); bool printRangePrefetchAlias(const MCInst *MI, const MCSubtargetInfo &STI, diff --git a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp index 36372c534ae78..268a22968f8ab 100644 --- a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp +++ b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp @@ -204,6 +204,27 @@ namespace AArch64MLBI { } // namespace AArch64MLBI } // namespace llvm +namespace llvm { +namespace AArch64GIC { +#define GET_GICTable_IMPL +#include "AArch64GenSystemOperands.inc" +} // namespace AArch64GIC +} // namespace llvm + +namespace llvm { +namespace AArch64GICR { +#define GET_GICRTable_IMPL +#include "AArch64GenSystemOperands.inc" +} // namespace AArch64GICR +} // namespace llvm + +namespace llvm { +namespace AArch64GSB { +#define GET_GSBTable_IMPL +#include "AArch64GenSystemOperands.inc" +} // namespace AArch64GSB +} // namespace llvm + namespace llvm { namespace AArch64SVCR { #define GET_SVCRsList_IMPL diff --git a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h index 15d1ad71cfdbc..27812e94a3516 100644 --- a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h +++ b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h @@ -829,6 +829,30 @@ struct MLBI : SysAliasReg { #include "AArch64GenSystemOperands.inc" } // namespace AArch64MLBI +namespace AArch64GIC { +struct GIC : SysAliasReg { + using SysAliasReg::SysAliasReg; +}; +#define GET_GICTable_DECL +#include "AArch64GenSystemOperands.inc" +} // namespace AArch64GIC + +namespace AArch64GICR { +struct GICR : SysAliasReg { + using SysAliasReg::SysAliasReg; +}; +#define GET_GICRTable_DECL +#include "AArch64GenSystemOperands.inc" +} // namespace AArch64GICR + +namespace AArch64GSB { +struct GSB : SysAlias { + using SysAlias::SysAlias; +}; +#define GET_GSBTable_DECL +#include "AArch64GenSystemOperands.inc" +} // namespace AArch64GSB + namespace AArch64II { /// Target Operand Flag enum. enum TOF { diff --git a/llvm/test/MC/AArch64/armv9.7a-gcie.s b/llvm/test/MC/AArch64/armv9.7a-gcie.s new file mode 100644 index 0000000000000..85e211f4c6be9 --- /dev/null +++ b/llvm/test/MC/AArch64/armv9.7a-gcie.s @@ -0,0 +1,985 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+gcie < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+all < %s \ +// RUN: | llvm-objdump -d --mattr=+gcie --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+all < %s \ +// RUN: | llvm-objdump -d --mattr=-gcie --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+gcie < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+gcie -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +//------------------------------------------------------------------------------ +// Armv9.7-A FEAT_GCIE Extensions +//------------------------------------------------------------------------------ + +// CPU Interface Registers MRS Instruction - Encodings Checked +MRS x3, ICC_APR_EL1 +// CHECK-INST: mrs x3, ICC_APR_EL1 +// CHECK-ENCODING: [0x03,0xc0,0x39,0xd5] +// CHECK-UNKNOWN: d539c003 + +MRS x3, ICC_APR_EL3 +// CHECK-INST: mrs x3, ICC_APR_EL3 +// CHECK-ENCODING: [0x03,0xc8,0x3e,0xd5] +// CHECK-UNKNOWN: d53ec803 + +MRS x3, ICC_CR0_EL1 +// CHECK-INST: mrs x3, ICC_CR0_EL1 +// CHECK-ENCODING: [0x23,0xc0,0x39,0xd5] +// CHECK-UNKNOWN: d539c023 + +MRS x3, ICC_CR0_EL3 +// CHECK-INST: mrs x3, ICC_CR0_EL3 +// CHECK-ENCODING: [0x03,0xc9,0x3e,0xd5] +// CHECK-UNKNOWN: d53ec903 + +MRS x3, ICC_DOMHPPIR_EL3 +// CHECK-INST: mrs x3, ICC_DOMHPPIR_EL3 +// CHECK-ENCODING: [0x43,0xc8,0x3e,0xd5] +// CHECK-UNKNOWN: d53ec843 + +MRS x3, ICC_HAPR_EL1 +// CHECK-INST: mrs x3, ICC_HAPR_EL1 +// CHECK-ENCODING: [0x63,0xc0,0x39,0xd5] +// CHECK-UNKNOWN: d539c063 + +MRS x3, ICC_HPPIR_EL1 +// CHECK-INST: mrs x3, ICC_HPPIR_EL1 +// CHECK-ENCODING: [0x63,0xca,0x38,0xd5] +// CHECK-UNKNOWN: d538ca63 + +MRS x3, ICC_HPPIR_EL3 +// CHECK-INST: mrs x3, ICC_HPPIR_EL3 +// CHECK-ENCODING: [0x23,0xc9,0x3e,0xd5] +// CHECK-UNKNOWN: d53ec923 + +MRS x3, ICC_IAFFIDR_EL1 +// CHECK-INST: mrs x3, ICC_IAFFIDR_EL1 +// CHECK-ENCODING: [0xa3,0xca,0x38,0xd5] +// CHECK-UNKNOWN: d538caa3 + +MRS x3, ICC_ICSR_EL1 +// CHECK-INST: mrs x3, ICC_ICSR_EL1 +// CHECK-ENCODING: [0x83,0xca,0x38,0xd5] +// CHECK-UNKNOWN: d538ca83 + +MRS x3, ICC_IDR0_EL1 +// CHECK-INST: mrs x3, ICC_IDR0_EL1 +// CHECK-ENCODING: [0x43,0xca,0x38,0xd5] +// CHECK-UNKNOWN: d538ca43 + +MRS x3, ICC_PCR_EL1 +// CHECK-INST: mrs x3, ICC_PCR_EL1 +// CHECK-ENCODING: [0x43,0xc0,0x39,0xd5] +// CHECK-UNKNOWN: d539c043 + +MRS x3, ICC_PCR_EL3 +// CHECK-INST: mrs x3, ICC_PCR_EL3 +// CHECK-ENCODING: [0x23,0xc8,0x3e,0xd5] +// CHECK-UNKNOWN: d53ec823 + +MRS x3, ICC_SRE_EL1 +// CHECK-INST: mrs x3, ICC_SRE_EL1 +// CHECK-ENCODING: [0xa3,0xcc,0x38,0xd5] +// CHECK-UNKNOWN: d538cca3 + +// ----------------------------------------------- +MSR ICC_APR_EL1, x3 +// CHECK-INST: msr ICC_APR_EL1, x3 +// CHECK-ENCODING: [0x03,0xc0,0x19,0xd5] +// CHECK-UNKNOWN: d519c003 + +MSR ICC_APR_EL3, x3 +// CHECK-INST: msr ICC_APR_EL3, x3 +// CHECK-ENCODING: [0x03,0xc8,0x1e,0xd5] +// CHECK-UNKNOWN: d51ec803 + +MSR ICC_CR0_EL1, x3 +// CHECK-INST: msr ICC_CR0_EL1, x3 +// CHECK-ENCODING: [0x23,0xc0,0x19,0xd5] +// CHECK-UNKNOWN: d519c023 + +MSR ICC_CR0_EL3, x3 +// CHECK-INST: msr ICC_CR0_EL3, x3 +// CHECK-ENCODING: [0x03,0xc9,0x1e,0xd5] +// CHECK-UNKNOWN: d51ec903 + +MSR ICC_ICSR_EL1, x3 +// CHECK-INST: msr ICC_ICSR_EL1, x3 +// CHECK-ENCODING: [0x83,0xca,0x18,0xd5] +// CHECK-UNKNOWN: d518ca83 + +MSR ICC_PCR_EL1, x3 +// CHECK-INST: msr ICC_PCR_EL1, x3 +// CHECK-ENCODING: [0x43,0xc0,0x19,0xd5] +// CHECK-UNKNOWN: d519c043 + +MSR ICC_PCR_EL3, x3 +// CHECK-INST: msr ICC_PCR_EL3, x3 +// CHECK-ENCODING: [0x23,0xc8,0x1e,0xd5] +// CHECK-UNKNOWN: d51ec823 + + +// ----------------------------------------------- +// Virtual CPU Registers MRS Instructions + +// The specification says: +// "Each ICC_system register that is accessible at EL1 and higher and whose state +// is specific to the Virtual Interrupt Domain, has a corresponding virtual +// ICV_register. The ICV_registers are accessed using the same system register +// encodings as their ICC_counterparts." +// +// So expect ICC_* encodings here, not ICV_* encodings + +MRS x3, ICV_APR_EL1 +// CHECK-INST: mrs x3, ICC_APR_EL1 +// CHECK-ENCODING: [0x03,0xc0,0x39,0xd5] +// CHECK-UNKNOWN: d539c003 + +MRS x3, ICV_CR0_EL1 +// CHECK-INST: mrs x3, ICC_CR0_EL1 +// CHECK-ENCODING: [0x23,0xc0,0x39,0xd5] +// CHECK-UNKNOWN: d539c023 + +MRS x3, ICV_HAPR_EL1 +// CHECK-INST: mrs x3, ICC_HAPR_EL1 +// CHECK-ENCODING: [0x63,0xc0,0x39,0xd5] +// CHECK-UNKNOWN: d539c063 + +MRS x3, ICV_HPPIR_EL1 +// CHECK-INST: mrs x3, ICC_HPPIR_EL1 +// CHECK-ENCODING: [0x63,0xca,0x38,0xd5] +// CHECK-UNKNOWN: d538ca63 + +MRS x3, ICV_PCR_EL1 +// CHECK-INST: mrs x3, ICC_PCR_EL1 +// CHECK-ENCODING: [0x43,0xc0,0x39,0xd5] +// CHECK-UNKNOWN: d539c043 + + +// ----------------------------------------------- +// Likewise here, expect ICC_* encodings here, not ICV_* encodings +MSR ICV_APR_EL1, x3 +// CHECK-INST: msr ICC_APR_EL1, x3 +// CHECK-ENCODING: [0x03,0xc0,0x19,0xd5] +// CHECK-UNKNOWN: d519c003 + +MSR ICV_CR0_EL1, x3 +// CHECK-INST: msr ICC_CR0_EL1, x3 +// CHECK-ENCODING: [0x23,0xc0,0x19,0xd5] +// CHECK-UNKNOWN: d519c023 + +MSR ICV_PCR_EL1, x3 +// CHECK-INST: msr ICC_PCR_EL1, x3 +// CHECK-ENCODING: [0x43,0xc0,0x19,0xd5] +// CHECK-UNKNOWN: d519c043 + +// ----------------------------------------------- +// PPI Registers MRS Instructions - Encodings Checked +MRS x3, ICC_PPI_CACTIVER0_EL1 +// CHECK-INST: mrs x3, ICC_PPI_CACTIVER0_EL1 +// CHECK-ENCODING: [0x03,0xcd,0x38,0xd5] +// CHECK-UNKNOWN: d538cd03 + +MRS x3, ICC_PPI_CACTIVER1_EL1 +// CHECK-INST: mrs x3, ICC_PPI_CACTIVER1_EL1 +// CHECK-ENCODING: [0x23,0xcd,0x38,0xd5] +// CHECK-UNKNOWN: d538cd23 + +MRS x3, ICC_PPI_CPENDR0_EL1 +// CHECK-INST: mrs x3, ICC_PPI_CPENDR0_EL1 +// CHECK-ENCODING: [0x83,0xcd,0x38,0xd5] +// CHECK-UNKNOWN: d538cd83 + +MRS x3, ICC_PPI_CPENDR1_EL1 +// CHECK-INST: mrs x3, ICC_PPI_CPENDR1_EL1 +// CHECK-ENCODING: [0xa3,0xcd,0x38,0xd5] +// CHECK-UNKNOWN: d538cda3 + +MRS x3, ICC_PPI_DOMAINR0_EL3 +// CHECK-INST: mrs x3, ICC_PPI_DOMAINR0_EL3 +// CHECK-ENCODING: [0x83,0xc8,0x3e,0xd5] +// CHECK-UNKNOWN: d53ec883 + +MRS x3, ICC_PPI_DOMAINR1_EL3 +// CHECK-INST: mrs x3, ICC_PPI_DOMAINR1_EL3 +// CHECK-ENCODING: [0xa3,0xc8,0x3e,0xd5] +// CHECK-UNKNOWN: d53ec8a3 + +MRS x3, ICC_PPI_DOMAINR2_EL3 +// CHECK-INST: mrs x3, ICC_PPI_DOMAINR2_EL3 +// CHECK-ENCODING: [0xc3,0xc8,0x3e,0xd5] +// CHECK-UNKNOWN: d53ec8c3 + +MRS x3, ICC_PPI_DOMAINR3_EL3 +// CHECK-INST: mrs x3, ICC_PPI_DOMAINR3_EL3 +// CHECK-ENCODING: [0xe3,0xc8,0x3e,0xd5] +// CHECK-UNKNOWN: d53ec8e3 + +MRS x3, ICC_PPI_ENABLER0_EL1 +// CHECK-INST: mrs x3, ICC_PPI_ENABLER0_EL1 +// CHECK-ENCODING: [0xc3,0xca,0x38,0xd5] +// CHECK-UNKNOWN: d538cac3 + +MRS x3, ICC_PPI_ENABLER1_EL1 +// CHECK-INST: mrs x3, ICC_PPI_ENABLER1_EL1 +// CHECK-ENCODING: [0xe3,0xca,0x38,0xd5] +// CHECK-UNKNOWN: d538cae3 + +MRS x3, ICC_PPI_PRIORITYR0_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR0_EL1 +// CHECK-ENCODING: [0x03,0xce,0x38,0xd5] +// CHECK-UNKNOWN: d538ce03 + +MRS x3, ICC_PPI_PRIORITYR1_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR1_EL1 +// CHECK-ENCODING: [0x23,0xce,0x38,0xd5] +// CHECK-UNKNOWN: d538ce23 + +MRS x3, ICC_PPI_PRIORITYR2_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR2_EL1 +// CHECK-ENCODING: [0x43,0xce,0x38,0xd5] +// CHECK-UNKNOWN: d538ce43 + +MRS x3, ICC_PPI_PRIORITYR3_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR3_EL1 +// CHECK-ENCODING: [0x63,0xce,0x38,0xd5] +// CHECK-UNKNOWN: d538ce63 + +MRS x3, ICC_PPI_PRIORITYR4_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR4_EL1 +// CHECK-ENCODING: [0x83,0xce,0x38,0xd5] +// CHECK-UNKNOWN: d538ce83 + +MRS x3, ICC_PPI_PRIORITYR5_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR5_EL1 +// CHECK-ENCODING: [0xa3,0xce,0x38,0xd5] +// CHECK-UNKNOWN: d538cea3 + +MRS x3, ICC_PPI_PRIORITYR6_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR6_EL1 +// CHECK-ENCODING: [0xc3,0xce,0x38,0xd5] +// CHECK-UNKNOWN: d538cec3 + +MRS x3, ICC_PPI_PRIORITYR7_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR7_EL1 +// CHECK-ENCODING: [0xe3,0xce,0x38,0xd5] +// CHECK-UNKNOWN: d538cee3 + +MRS x3, ICC_PPI_PRIORITYR8_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR8_EL1 +// CHECK-ENCODING: [0x03,0xcf,0x38,0xd5] +// CHECK-UNKNOWN: d538cf03 + +MRS x3, ICC_PPI_PRIORITYR9_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR9_EL1 +// CHECK-ENCODING: [0x23,0xcf,0x38,0xd5] +// CHECK-UNKNOWN: d538cf23 + +MRS x3, ICC_PPI_PRIORITYR10_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR10_EL1 +// CHECK-ENCODING: [0x43,0xcf,0x38,0xd5] +// CHECK-UNKNOWN: d538cf43 + +MRS x3, ICC_PPI_PRIORITYR11_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR11_EL1 +// CHECK-ENCODING: [0x63,0xcf,0x38,0xd5] +// CHECK-UNKNOWN: d538cf63 + +MRS x3, ICC_PPI_PRIORITYR12_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR12_EL1 +// CHECK-ENCODING: [0x83,0xcf,0x38,0xd5] +// CHECK-UNKNOWN: d538cf83 + +MRS x3, ICC_PPI_PRIORITYR13_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR13_EL1 +// CHECK-ENCODING: [0xa3,0xcf,0x38,0xd5] +// CHECK-UNKNOWN: d538cfa3 + +MRS x3, ICC_PPI_PRIORITYR14_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR14_EL1 +// CHECK-ENCODING: [0xc3,0xcf,0x38,0xd5] +// CHECK-UNKNOWN: d538cfc3 + +MRS x3, ICC_PPI_PRIORITYR15_EL1 +// CHECK-INST: mrs x3, ICC_PPI_PRIORITYR15_EL1 +// CHECK-ENCODING: [0xe3,0xcf,0x38,0xd5] +// CHECK-UNKNOWN: d538cfe3 + +MRS x3, ICC_PPI_SACTIVER0_EL1 +// CHECK-INST: mrs x3, ICC_PPI_SACTIVER0_EL1 +// CHECK-ENCODING: [0x43,0xcd,0x38,0xd5] +// CHECK-UNKNOWN: d538cd43 + +MRS x3, ICC_PPI_SACTIVER1_EL1 +// CHECK-INST: mrs x3, ICC_PPI_SACTIVER1_EL1 +// CHECK-ENCODING: [0x63,0xcd,0x38,0xd5] +// CHECK-UNKNOWN: d538cd63 + +MRS x3, ICC_PPI_SPENDR0_EL1 +// CHECK-INST: mrs x3, ICC_PPI_SPENDR0_EL1 +// CHECK-ENCODING: [0xc3,0xcd,0x38,0xd5] +// CHECK-UNKNOWN: d538cdc3 + +MRS x3, ICC_PPI_SPENDR1_EL1 +// CHECK-INST: mrs x3, ICC_PPI_SPENDR1_EL1 +// CHECK-ENCODING: [0xe3,0xcd,0x38,0xd5] +// CHECK-UNKNOWN: d538cde3 + +MRS x3, ICC_PPI_HMR0_EL1 +// CHECK-INST: mrs x3, ICC_PPI_HMR0_EL1 +// CHECK-ENCODING: [0x03,0xca,0x38,0xd5] +// CHECK-UNKNOWN: d538ca03 + +MRS x3, ICC_PPI_HMR1_EL1 +// CHECK-INST: mrs x3, ICC_PPI_HMR1_EL1 +// CHECK-ENCODING: [0x23,0xca,0x38,0xd5] +// CHECK-UNKNOWN: d538ca23 + +// ----------------------------------------------- +// MSR PPI Registers Instructions +MSR ICC_PPI_CACTIVER0_EL1, x3 +// CHECK-INST: msr ICC_PPI_CACTIVER0_EL1, x3 +// CHECK-ENCODING: [0x03,0xcd,0x18,0xd5] +// CHECK-UNKNOWN: d518cd03 + +MSR ICC_PPI_CACTIVER1_EL1, x3 +// CHECK-INST: msr ICC_PPI_CACTIVER1_EL1, x3 +// CHECK-ENCODING: [0x23,0xcd,0x18,0xd5] +// CHECK-UNKNOWN: d518cd23 + +MSR ICC_PPI_CPENDR0_EL1, x3 +// CHECK-INST: msr ICC_PPI_CPENDR0_EL1, x3 +// CHECK-ENCODING: [0x83,0xcd,0x18,0xd5] +// CHECK-UNKNOWN: d518cd83 + +MSR ICC_PPI_CPENDR1_EL1, x3 +// CHECK-INST: msr ICC_PPI_CPENDR1_EL1, x3 +// CHECK-ENCODING: [0xa3,0xcd,0x18,0xd5] +// CHECK-UNKNOWN: d518cda3 + +MSR ICC_PPI_DOMAINR0_EL3, x3 +// CHECK-INST: msr ICC_PPI_DOMAINR0_EL3, x3 +// CHECK-ENCODING: [0x83,0xc8,0x1e,0xd5] +// CHECK-UNKNOWN: d51ec883 + +MSR ICC_PPI_DOMAINR1_EL3, x3 +// CHECK-INST: msr ICC_PPI_DOMAINR1_EL3, x3 +// CHECK-ENCODING: [0xa3,0xc8,0x1e,0xd5] +// CHECK-UNKNOWN: d51ec8a3 + +MSR ICC_PPI_DOMAINR2_EL3, x3 +// CHECK-INST: msr ICC_PPI_DOMAINR2_EL3, x3 +// CHECK-ENCODING: [0xc3,0xc8,0x1e,0xd5] +// CHECK-UNKNOWN: d51ec8c3 + +MSR ICC_PPI_DOMAINR3_EL3, x3 +// CHECK-INST: msr ICC_PPI_DOMAINR3_EL3, x3 +// CHECK-ENCODING: [0xe3,0xc8,0x1e,0xd5] +// CHECK-UNKNOWN: d51ec8e3 + +MSR ICC_PPI_ENABLER0_EL1, x3 +// CHECK-INST: msr ICC_PPI_ENABLER0_EL1, x3 +// CHECK-ENCODING: [0xc3,0xca,0x18,0xd5] +// CHECK-UNKNOWN: d518cac3 + +MSR ICC_PPI_ENABLER1_EL1, x3 +// CHECK-INST: msr ICC_PPI_ENABLER1_EL1, x3 +// CHECK-ENCODING: [0xe3,0xca,0x18,0xd5] +// CHECK-UNKNOWN: d518cae3 + +MSR ICC_PPI_PRIORITYR0_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR0_EL1, x3 +// CHECK-ENCODING: [0x03,0xce,0x18,0xd5] +// CHECK-UNKNOWN: d518ce03 + +MSR ICC_PPI_PRIORITYR1_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR1_EL1, x3 +// CHECK-ENCODING: [0x23,0xce,0x18,0xd5] +// CHECK-UNKNOWN: d518ce23 + +MSR ICC_PPI_PRIORITYR2_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR2_EL1, x3 +// CHECK-ENCODING: [0x43,0xce,0x18,0xd5] +// CHECK-UNKNOWN: d518ce43 + +MSR ICC_PPI_PRIORITYR3_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR3_EL1, x3 +// CHECK-ENCODING: [0x63,0xce,0x18,0xd5] +// CHECK-UNKNOWN: d518ce63 + +MSR ICC_PPI_PRIORITYR4_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR4_EL1, x3 +// CHECK-ENCODING: [0x83,0xce,0x18,0xd5] +// CHECK-UNKNOWN: d518ce83 + +MSR ICC_PPI_PRIORITYR5_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR5_EL1, x3 +// CHECK-ENCODING: [0xa3,0xce,0x18,0xd5] +// CHECK-UNKNOWN: d518cea3 + +MSR ICC_PPI_PRIORITYR6_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR6_EL1, x3 +// CHECK-ENCODING: [0xc3,0xce,0x18,0xd5] +// CHECK-UNKNOWN: d518cec3 + +MSR ICC_PPI_PRIORITYR7_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR7_EL1, x3 +// CHECK-ENCODING: [0xe3,0xce,0x18,0xd5] +// CHECK-UNKNOWN: d518cee3 + +MSR ICC_PPI_PRIORITYR8_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR8_EL1, x3 +// CHECK-ENCODING: [0x03,0xcf,0x18,0xd5] +// CHECK-UNKNOWN: d518cf03 + +MSR ICC_PPI_PRIORITYR9_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR9_EL1, x3 +// CHECK-ENCODING: [0x23,0xcf,0x18,0xd5] +// CHECK-UNKNOWN: d518cf23 + +MSR ICC_PPI_PRIORITYR10_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR10_EL1, x3 +// CHECK-ENCODING: [0x43,0xcf,0x18,0xd5] +// CHECK-UNKNOWN: d518cf43 + +MSR ICC_PPI_PRIORITYR11_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR11_EL1, x3 +// CHECK-ENCODING: [0x63,0xcf,0x18,0xd5] +// CHECK-UNKNOWN: d518cf63 + +MSR ICC_PPI_PRIORITYR12_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR12_EL1, x3 +// CHECK-ENCODING: [0x83,0xcf,0x18,0xd5] +// CHECK-UNKNOWN: d518cf83 + +MSR ICC_PPI_PRIORITYR13_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR13_EL1, x3 +// CHECK-ENCODING: [0xa3,0xcf,0x18,0xd5] +// CHECK-UNKNOWN: d518cfa3 + +MSR ICC_PPI_PRIORITYR14_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR14_EL1, x3 +// CHECK-ENCODING: [0xc3,0xcf,0x18,0xd5] +// CHECK-UNKNOWN: d518cfc3 + +MSR ICC_PPI_PRIORITYR15_EL1, x3 +// CHECK-INST: msr ICC_PPI_PRIORITYR15_EL1, x3 +// CHECK-ENCODING: [0xe3,0xcf,0x18,0xd5] +// CHECK-UNKNOWN: d518cfe3 + +MSR ICC_PPI_SACTIVER0_EL1, x3 +// CHECK-INST: msr ICC_PPI_SACTIVER0_EL1, x3 +// CHECK-ENCODING: [0x43,0xcd,0x18,0xd5] +// CHECK-UNKNOWN: d518cd43 + +MSR ICC_PPI_SACTIVER1_EL1, x3 +// CHECK-INST: msr ICC_PPI_SACTIVER1_EL1, x3 +// CHECK-ENCODING: [0x63,0xcd,0x18,0xd5] +// CHECK-UNKNOWN: d518cd63 + +MSR ICC_PPI_SPENDR0_EL1, x3 +// CHECK-INST: msr ICC_PPI_SPENDR0_EL1, x3 +// CHECK-ENCODING: [0xc3,0xcd,0x18,0xd5] +// CHECK-UNKNOWN: d518cdc3 + +MSR ICC_PPI_SPENDR1_EL1, x3 +// CHECK-INST: msr ICC_PPI_SPENDR1_EL1, x3 +// CHECK-ENCODING: [0xe3,0xcd,0x18,0xd5] +// CHECK-UNKNOWN: d518cde3 + +// ----------------------------------------------- +// Hypervisor Control Register MRS Instructions +MRS x3, ICH_APR_EL2 +// CHECK-INST: mrs x3, ICH_APR_EL2 +// CHECK-ENCODING: [0x83,0xc8,0x3c,0xd5] +// CHECK-UNKNOWN: d53cc883 + +MRS x3, ICH_CONTEXTR_EL2 +// CHECK-INST: mrs x3, ICH_CONTEXTR_EL2 +// CHECK-ENCODING: [0xc3,0xcb,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccbc3 + +MRS x3, ICH_HFGITR_EL2 +// CHECK-INST: mrs x3, ICH_HFGITR_EL2 +// CHECK-ENCODING: [0xe3,0xc9,0x3c,0xd5] +// CHECK-UNKNOWN: d53cc9e3 + +MRS x3, ICH_HFGRTR_EL2 +// CHECK-INST: mrs x3, ICH_HFGRTR_EL2 +// CHECK-ENCODING: [0x83,0xc9,0x3c,0xd5] +// CHECK-UNKNOWN: d53cc983 + +MRS x3, ICH_HFGWTR_EL2 +// CHECK-INST: mrs x3, ICH_HFGWTR_EL2 +// CHECK-ENCODING: [0xc3,0xc9,0x3c,0xd5] +// CHECK-UNKNOWN: d53cc9c3 + +MRS x3, ICH_HPPIR_EL2 +// CHECK-INST: mrs x3, ICH_HPPIR_EL2 +// CHECK-ENCODING: [0xa3,0xc8,0x3c,0xd5] +// CHECK-UNKNOWN: d53cc8a3 + +MRS x3, ICH_PPI_ACTIVER0_EL2 +// CHECK-INST: mrs x3, ICH_PPI_ACTIVER0_EL2 +// CHECK-ENCODING: [0xc3,0xca,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccac3 + +MRS x3, ICH_PPI_ACTIVER1_EL2 +// CHECK-INST: mrs x3, ICH_PPI_ACTIVER1_EL2 +// CHECK-ENCODING: [0xe3,0xca,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccae3 + +MRS x3, ICH_PPI_DVIR0_EL2 +// CHECK-INST: mrs x3, ICH_PPI_DVIR0_EL2 +// CHECK-ENCODING: [0x03,0xca,0x3c,0xd5] +// CHECK-UNKNOWN: d53cca03 + +MRS x3, ICH_PPI_DVIR1_EL2 +// CHECK-INST: mrs x3, ICH_PPI_DVIR1_EL2 +// CHECK-ENCODING: [0x23,0xca,0x3c,0xd5] +// CHECK-UNKNOWN: d53cca23 + +MRS x3, ICH_PPI_ENABLER0_EL2 +// CHECK-INST: mrs x3, ICH_PPI_ENABLER0_EL2 +// CHECK-ENCODING: [0x43,0xca,0x3c,0xd5] +// CHECK-UNKNOWN: d53cca43 + +MRS x3, ICH_PPI_ENABLER1_EL2 +// CHECK-INST: mrs x3, ICH_PPI_ENABLER1_EL2 +// CHECK-ENCODING: [0x63,0xca,0x3c,0xd5] +// CHECK-UNKNOWN: d53cca63 + +MRS x3, ICH_PPI_PENDR0_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PENDR0_EL2 +// CHECK-ENCODING: [0x83,0xca,0x3c,0xd5] +// CHECK-UNKNOWN: d53cca83 + +MRS x3, ICH_PPI_PENDR1_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PENDR1_EL2 +// CHECK-ENCODING: [0xa3,0xca,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccaa3 + +MRS x3, ICH_PPI_PRIORITYR0_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR0_EL2 +// CHECK-ENCODING: [0x03,0xce,0x3c,0xd5] +// CHECK-UNKNOWN: d53cce03 + +MRS x3, ICH_PPI_PRIORITYR1_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR1_EL2 +// CHECK-ENCODING: [0x23,0xce,0x3c,0xd5] +// CHECK-UNKNOWN: d53cce23 + +MRS x3, ICH_PPI_PRIORITYR2_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR2_EL2 +// CHECK-ENCODING: [0x43,0xce,0x3c,0xd5] +// CHECK-UNKNOWN: d53cce43 + +MRS x3, ICH_PPI_PRIORITYR3_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR3_EL2 +// CHECK-ENCODING: [0x63,0xce,0x3c,0xd5] +// CHECK-UNKNOWN: d53cce63 + +MRS x3, ICH_PPI_PRIORITYR4_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR4_EL2 +// CHECK-ENCODING: [0x83,0xce,0x3c,0xd5] +// CHECK-UNKNOWN: d53cce83 + +MRS x3, ICH_PPI_PRIORITYR5_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR5_EL2 +// CHECK-ENCODING: [0xa3,0xce,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccea3 + +MRS x3, ICH_PPI_PRIORITYR6_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR6_EL2 +// CHECK-ENCODING: [0xc3,0xce,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccec3 + +MRS x3, ICH_PPI_PRIORITYR7_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR7_EL2 +// CHECK-ENCODING: [0xe3,0xce,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccee3 + +MRS x3, ICH_PPI_PRIORITYR8_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR8_EL2 +// CHECK-ENCODING: [0x03,0xcf,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccf03 + +MRS x3, ICH_PPI_PRIORITYR9_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR9_EL2 +// CHECK-ENCODING: [0x23,0xcf,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccf23 + +MRS x3, ICH_PPI_PRIORITYR10_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR10_EL2 +// CHECK-ENCODING: [0x43,0xcf,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccf43 + +MRS x3, ICH_PPI_PRIORITYR11_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR11_EL2 +// CHECK-ENCODING: [0x63,0xcf,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccf63 + +MRS x3, ICH_PPI_PRIORITYR12_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR12_EL2 +// CHECK-ENCODING: [0x83,0xcf,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccf83 + +MRS x3, ICH_PPI_PRIORITYR13_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR13_EL2 +// CHECK-ENCODING: [0xa3,0xcf,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccfa3 + +MRS x3, ICH_PPI_PRIORITYR14_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR14_EL2 +// CHECK-ENCODING: [0xc3,0xcf,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccfc3 + +MRS x3, ICH_PPI_PRIORITYR15_EL2 +// CHECK-INST: mrs x3, ICH_PPI_PRIORITYR15_EL2 +// CHECK-ENCODING: [0xe3,0xcf,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccfe3 + +MRS x3, ICH_VCTLR_EL2 +// CHECK-INST: mrs x3, ICH_VCTLR_EL2 +// CHECK-ENCODING: [0x83,0xcb,0x3c,0xd5] +// CHECK-UNKNOWN: d53ccb83 + +// ----------------------------------------------- +// Hypervisor Control Register MSR Instructions +MSR ICH_APR_EL2, x3 +// CHECK-INST: msr ICH_APR_EL2, x3 +// CHECK-ENCODING: [0x83,0xc8,0x1c,0xd5] +// CHECK-UNKNOWN: d51cc883 + +MSR ICH_CONTEXTR_EL2, x3 +// CHECK-INST: msr ICH_CONTEXTR_EL2, x3 +// CHECK-ENCODING: [0xc3,0xcb,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccbc3 + +MSR ICH_HFGITR_EL2, x3 +// CHECK-INST: msr ICH_HFGITR_EL2, x3 +// CHECK-ENCODING: [0xe3,0xc9,0x1c,0xd5] +// CHECK-UNKNOWN: d51cc9e3 + +MSR ICH_HFGRTR_EL2, x3 +// CHECK-INST: msr ICH_HFGRTR_EL2, x3 +// CHECK-ENCODING: [0x83,0xc9,0x1c,0xd5] +// CHECK-UNKNOWN: d51cc983 + +MSR ICH_HFGWTR_EL2, x3 +// CHECK-INST: msr ICH_HFGWTR_EL2, x3 +// CHECK-ENCODING: [0xc3,0xc9,0x1c,0xd5] +// CHECK-UNKNOWN: d51cc9c3 + +MSR ICH_PPI_ACTIVER0_EL2, x3 +// CHECK-INST: msr ICH_PPI_ACTIVER0_EL2, x3 +// CHECK-ENCODING: [0xc3,0xca,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccac3 + +MSR ICH_PPI_ACTIVER1_EL2, x3 +// CHECK-INST: msr ICH_PPI_ACTIVER1_EL2, x3 +// CHECK-ENCODING: [0xe3,0xca,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccae3 + +MSR ICH_PPI_DVIR0_EL2, x3 +// CHECK-INST: msr ICH_PPI_DVIR0_EL2, x3 +// CHECK-ENCODING: [0x03,0xca,0x1c,0xd5] +// CHECK-UNKNOWN: d51cca03 + +MSR ICH_PPI_DVIR1_EL2, x3 +// CHECK-INST: msr ICH_PPI_DVIR1_EL2, x3 +// CHECK-ENCODING: [0x23,0xca,0x1c,0xd5] +// CHECK-UNKNOWN: d51cca23 + +MSR ICH_PPI_ENABLER0_EL2, x3 +// CHECK-INST: msr ICH_PPI_ENABLER0_EL2, x3 +// CHECK-ENCODING: [0x43,0xca,0x1c,0xd5] +// CHECK-UNKNOWN: d51cca43 + +MSR ICH_PPI_ENABLER1_EL2, x3 +// CHECK-INST: msr ICH_PPI_ENABLER1_EL2, x3 +// CHECK-ENCODING: [0x63,0xca,0x1c,0xd5] +// CHECK-UNKNOWN: d51cca63 + +MSR ICH_PPI_PENDR0_EL2, x3 +// CHECK-INST: msr ICH_PPI_PENDR0_EL2, x3 +// CHECK-ENCODING: [0x83,0xca,0x1c,0xd5] +// CHECK-UNKNOWN: d51cca83 + +MSR ICH_PPI_PENDR1_EL2, x3 +// CHECK-INST: msr ICH_PPI_PENDR1_EL2, x3 +// CHECK-ENCODING: [0xa3,0xca,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccaa3 + +MSR ICH_PPI_PRIORITYR0_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR0_EL2, x3 +// CHECK-ENCODING: [0x03,0xce,0x1c,0xd5] +// CHECK-UNKNOWN: d51cce03 + +MSR ICH_PPI_PRIORITYR1_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR1_EL2, x3 +// CHECK-ENCODING: [0x23,0xce,0x1c,0xd5] +// CHECK-UNKNOWN: d51cce23 + +MSR ICH_PPI_PRIORITYR2_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR2_EL2, x3 +// CHECK-ENCODING: [0x43,0xce,0x1c,0xd5] +// CHECK-UNKNOWN: d51cce43 + +MSR ICH_PPI_PRIORITYR3_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR3_EL2, x3 +// CHECK-ENCODING: [0x63,0xce,0x1c,0xd5] +// CHECK-UNKNOWN: d51cce63 + +MSR ICH_PPI_PRIORITYR4_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR4_EL2, x3 +// CHECK-ENCODING: [0x83,0xce,0x1c,0xd5] +// CHECK-UNKNOWN: d51cce83 + +MSR ICH_PPI_PRIORITYR5_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR5_EL2, x3 +// CHECK-ENCODING: [0xa3,0xce,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccea3 + +MSR ICH_PPI_PRIORITYR6_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR6_EL2, x3 +// CHECK-ENCODING: [0xc3,0xce,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccec3 + +MSR ICH_PPI_PRIORITYR7_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR7_EL2, x3 +// CHECK-ENCODING: [0xe3,0xce,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccee3 + +MSR ICH_PPI_PRIORITYR8_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR8_EL2, x3 +// CHECK-ENCODING: [0x03,0xcf,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccf03 + +MSR ICH_PPI_PRIORITYR9_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR9_EL2, x3 +// CHECK-ENCODING: [0x23,0xcf,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccf23 + +MSR ICH_PPI_PRIORITYR10_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR10_EL2, x3 +// CHECK-ENCODING: [0x43,0xcf,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccf43 + +MSR ICH_PPI_PRIORITYR11_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR11_EL2, x3 +// CHECK-ENCODING: [0x63,0xcf,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccf63 + +MSR ICH_PPI_PRIORITYR12_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR12_EL2, x3 +// CHECK-ENCODING: [0x83,0xcf,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccf83 + +MSR ICH_PPI_PRIORITYR13_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR13_EL2, x3 +// CHECK-ENCODING: [0xa3,0xcf,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccfa3 + +MSR ICH_PPI_PRIORITYR14_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR14_EL2, x3 +// CHECK-ENCODING: [0xc3,0xcf,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccfc3 + +MSR ICH_PPI_PRIORITYR15_EL2, x3 +// CHECK-INST: msr ICH_PPI_PRIORITYR15_EL2, x3 +// CHECK-ENCODING: [0xe3,0xcf,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccfe3 + +MSR ICH_VCTLR_EL2, x3 +// CHECK-INST: msr ICH_VCTLR_EL2, x3 +// CHECK-ENCODING: [0x83,0xcb,0x1c,0xd5] +// CHECK-UNKNOWN: d51ccb83 + +// ----------------------------------------------- +// FEAT_GCIE Instructions +// Current Interrupt Domain +GIC CDAFF, x3 +// CHECK-INST: gic cdaff, x3 +// CHECK-ENCODING: [0x63,0xc1,0x08,0xd5] +// CHECK-UNKNOWN: d508c163 sys #0, c12, c1, #3, x3 +// CHECK-ERROR: error: GIC cdaff requires: gcie + +GIC CDDI, x3 +// CHECK-INST: gic cddi, x3 +// CHECK-ENCODING: [0x03,0xc2,0x08,0xd5] +// CHECK-UNKNOWN: d508c203 sys #0, c12, c2, #0, x3 +// CHECK-ERROR: error: GIC cddi requires: gcie + +GIC CDDIS, x3 +// CHECK-INST: gic cddis, x3 +// CHECK-ENCODING: [0x03,0xc1,0x08,0xd5] +// CHECK-UNKNOWN: d508c103 sys #0, c12, c1, #0, x3 +// CHECK-ERROR: error: GIC cddis requires: gcie + +GIC CDEN, x3 +// CHECK-INST: gic cden, x3 +// CHECK-ENCODING: [0x23,0xc1,0x08,0xd5] +// CHECK-UNKNOWN: d508c123 sys #0, c12, c1, #1, x3 +// CHECK-ERROR: error: GIC cden requires: gcie + +GIC CDEOI, x3 +// CHECK-INST: gic cdeoi, x3 +// CHECK-ENCODING: [0xe3,0xc1,0x08,0xd5] +// CHECK-UNKNOWN: d508c1e3 sys #0, c12, c1, #7, x3 +// CHECK-ERROR: error: GIC cdeoi requires: gcie + +GIC CDHM, x3 +// CHECK-INST: gic cdhm, x3 +// CHECK-ENCODING: [0x23,0xc2,0x08,0xd5] +// CHECK-UNKNOWN: d508c223 sys #0, c12, c2, #1, x3 +// CHECK-ERROR: error: GIC cdhm requires: gcie + +GIC CDPEND, x3 +// CHECK-INST: gic cdpend, x3 +// CHECK-ENCODING: [0x83,0xc1,0x08,0xd5] +// CHECK-UNKNOWN: d508c183 sys #0, c12, c1, #4, x3 +// CHECK-ERROR: error: GIC cdpend requires: gcie + +GIC CDPRI, x3 +// CHECK-INST: gic cdpri, x3 +// CHECK-ENCODING: [0x43,0xc1,0x08,0xd5] +// CHECK-UNKNOWN: d508c143 sys #0, c12, c1, #2, x3 +// CHECK-ERROR: error: GIC cdpri requires: gcie + +GIC CDRCFG, x3 +// CHECK-INST: gic cdrcfg, x3 +// CHECK-ENCODING: [0xa3,0xc1,0x08,0xd5] +// CHECK-UNKNOWN: d508c1a3 sys #0, c12, c1, #5, x3 +// CHECK-ERROR: error: GIC cdrcfg requires: gcie + +GICR x3, CDIA +// CHECK-INST: gicr x3, cdia +// CHECK-ENCODING: [0x03,0xc3,0x28,0xd5] +// CHECK-UNKNOWN: d528c303 sysl x3, #0, c12, c3, #0 +// CHECK-ERROR: error: GICR cdia requires: gcie + +GICR x3, CDNMIA +// CHECK-INST: gicr x3, cdnmia +// CHECK-ENCODING: [0x23,0xc3,0x28,0xd5] +// CHECK-UNKNOWN: d528c323 sysl x3, #0, c12, c3, #1 +// CHECK-ERROR: error: GICR cdnmia requires: gcie + +// ----------------------------------------------- +// Virtual Interrupt Domain +GIC VDAFF, x3 +// CHECK-INST: gic vdaff, x3 +// CHECK-ENCODING: [0x63,0xc1,0x0c,0xd5] +// CHECK-UNKNOWN: d50cc163 sys #4, c12, c1, #3, x3 +// CHECK-ERROR: error: GIC vdaff requires: gcie + +GIC VDDI, x3 +// CHECK-INST: gic vddi, x3 +// CHECK-ENCODING: [0x03,0xc2,0x0c,0xd5] +// CHECK-UNKNOWN: d50cc203 sys #4, c12, c2, #0, x3 +// CHECK-ERROR: error: GIC vddi requires: gcie + +GIC VDDIS, x3 +// CHECK-INST: gic vddis, x3 +// CHECK-ENCODING: [0x03,0xc1,0x0c,0xd5] +// CHECK-UNKNOWN: d50cc103 sys #4, c12, c1, #0, x3 +// CHECK-ERROR: error: GIC vddis requires: gcie + +GIC VDEN, x3 +// CHECK-INST: gic vden, x3 +// CHECK-ENCODING: [0x23,0xc1,0x0c,0xd5] +// CHECK-UNKNOWN: d50cc123 sys #4, c12, c1, #1, x3 +// CHECK-ERROR: error: GIC vden requires: gcie + +GIC VDHM, x3 +// CHECK-INST: gic vdhm, x3 +// CHECK-ENCODING: [0x23,0xc2,0x0c,0xd5] +// CHECK-UNKNOWN: d50cc223 sys #4, c12, c2, #1, x3 +// CHECK-ERROR: error: GIC vdhm requires: gcie + +GIC VDPEND, x3 +// CHECK-INST: gic vdpend, x3 +// CHECK-ENCODING: [0x83,0xc1,0x0c,0xd5] +// CHECK-UNKNOWN: d50cc183 sys #4, c12, c1, #4, x3 +// CHECK-ERROR: error: GIC vdpend requires: gcie + +GIC VDPRI, x3 +// CHECK-INST: gic vdpri, x3 +// CHECK-ENCODING: [0x43,0xc1,0x0c,0xd5] +// CHECK-UNKNOWN: d50cc143 sys #4, c12, c1, #2, x3 +// CHECK-ERROR: error: GIC vdpri requires: gcie + +GIC VDRCFG, x3 +// CHECK-INST: gic vdrcfg, x3 +// CHECK-ENCODING: [0xa3,0xc1,0x0c,0xd5] +// CHECK-UNKNOWN: d50cc1a3 sys #4, c12, c1, #5, x3 +// CHECK-ERROR: error: GIC vdrcfg requires: gcie + +// ----------------------------------------------- +// Logical Interrupt Domain +GIC LDAFF, x3 +// CHECK-INST: gic ldaff, x3 +// CHECK-ENCODING: [0x63,0xc1,0x0e,0xd5] +// CHECK-UNKNOWN: d50ec163 sys #6, c12, c1, #3, x3 +// CHECK-ERROR: error: GIC ldaff requires: gcie + +GIC LDDI, x3 +// CHECK-INST: gic lddi, x3 +// CHECK-ENCODING: [0x03,0xc2,0x0e,0xd5] +// CHECK-UNKNOWN: d50ec203 sys #6, c12, c2, #0, x3 +// CHECK-ERROR: error: GIC lddi requires: gcie + +GIC LDDIS, x3 +// CHECK-INST: gic lddis, x3 +// CHECK-ENCODING: [0x03,0xc1,0x0e,0xd5] +// CHECK-UNKNOWN: d50ec103 sys #6, c12, c1, #0, x3 +// CHECK-ERROR: error: GIC lddis requires: gcie + +GIC LDEN, x3 +// CHECK-INST: gic lden, x3 +// CHECK-ENCODING: [0x23,0xc1,0x0e,0xd5] +// CHECK-UNKNOWN: d50ec123 sys #6, c12, c1, #1, x3 +// CHECK-ERROR: error: GIC lden requires: gcie + +GIC LDHM, x3 +// CHECK-INST: gic ldhm, x3 +// CHECK-ENCODING: [0x23,0xc2,0x0e,0xd5] +// CHECK-UNKNOWN: d50ec223 sys #6, c12, c2, #1, x3 +// CHECK-ERROR: error: GIC ldhm requires: gcie + +GIC LDPEND, x3 +// CHECK-INST: gic ldpend, x3 +// CHECK-ENCODING: [0x83,0xc1,0x0e,0xd5] +// CHECK-UNKNOWN: d50ec183 sys #6, c12, c1, #4, x3 +// CHECK-ERROR: error: GIC ldpend requires: gcie + +GIC LDPRI, x3 +// CHECK-INST: gic ldpri, x3 +// CHECK-ENCODING: [0x43,0xc1,0x0e,0xd5] +// CHECK-UNKNOWN: d50ec143 sys #6, c12, c1, #2, x3 +// CHECK-ERROR: error: GIC ldpri requires: gcie + +GIC LDRCFG, x3 +// CHECK-INST: gic ldrcfg, x3 +// CHECK-ENCODING: [0xa3,0xc1,0x0e,0xd5] +// CHECK-UNKNOWN: d50ec1a3 sys #6, c12, c1, #5, x3 +// CHECK-ERROR: error: GIC ldrcfg requires: gcie + +// ----------------------------------------------- +// GIC Synchronization Barrier Instructions +GSB SYS +// CHECK-INST: gsb sys +// CHECK-ENCODING: [0x1f,0xc0,0x08,0xd5] +// CHECK-UNKNOWN: d508c01f sys #0, c12, c0, #0 +// CHECK-ERROR: error: GSB sys requires: gcie + +GSB ACK +// CHECK-INST: gsb ack +// CHECK-ENCODING: [0x3f,0xc0,0x08,0xd5] +// CHECK-UNKNOWN: d508c03f sys #0, c12, c0, #1 +// CHECK-ERROR: error: GSB ack requires: gcie diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index fdf937fa8cfdc..5a14e01d21e6a 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1446,6 +1446,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) { AArch64::AEK_SVESM4, AArch64::AEK_CMH, AArch64::AEK_LSCP, AArch64::AEK_TLBID, AArch64::AEK_MPAMV2, AArch64::AEK_MTETC, + AArch64::AEK_GCIE, }; std::vector<StringRef> Features; @@ -1562,6 +1563,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) { EXPECT_TRUE(llvm::is_contained(Features, "+tlbid")); EXPECT_TRUE(llvm::is_contained(Features, "+mpamv2")); EXPECT_TRUE(llvm::is_contained(Features, "+mtetc")); + EXPECT_TRUE(llvm::is_contained(Features, "+gcie")); // Assuming we listed every extension above, this should produce the same // result. @@ -1733,6 +1735,7 @@ TEST(TargetParserTest, AArch64ArchExtFeature) { {"tlbid", "notlbid", "+tlbid", "-tlbid"}, {"mpamv2", "nompamv2", "+mpamv2", "-mpamv2"}, {"mtetc", "nomtetc", "+mtetc", "-mtetc"}, + {"gcie", "nogcie", "+gcie", "-gcie"}, }; for (unsigned i = 0; i < std::size(ArchExt); i++) { >From 6df67419f3ca140f7c6c555c400728fa88226d14 Mon Sep 17 00:00:00 2001 From: Jonathan Thackray <[email protected]> Date: Mon, 13 Oct 2025 18:59:12 +0100 Subject: [PATCH 2/3] fixup! [AArch64][llvm] Armv9.7-A: Add support for GICv5 (FEAT_GCIE) Move FEAT_GCIE from VFAT --- clang/test/Driver/aarch64-v97a.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/clang/test/Driver/aarch64-v97a.c b/clang/test/Driver/aarch64-v97a.c index 008f79e11e18c..8518d6b069556 100644 --- a/clang/test/Driver/aarch64-v97a.c +++ b/clang/test/Driver/aarch64-v97a.c @@ -38,6 +38,6 @@ // RUN: %clang -target aarch64 -march=armv9.7-a+mtetc -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MTETC %s // V97A-MTETC: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+mtetc" -// RUN: %clang -target aarch64 -march=armv9.7a+gcie -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-GCIE %s -// RUN: %clang -target aarch64 -march=armv9.7-a+gcie -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-GCIE %s -// VFAT-GCIE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+gcie" +// RUN: %clang -target aarch64 -march=armv9.7a+gcie -### -c %s 2>&1 | FileCheck -check-prefix=V97A-GCIE %s +// RUN: %clang -target aarch64 -march=armv9.7-a+gcie -### -c %s 2>&1 | FileCheck -check-prefix=V97A-GCIE %s +// V97A-GCIE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+gcie" >From d42c5df4209a486ac8431eb2c44d77c8ee4fcb31 Mon Sep 17 00:00:00 2001 From: Jonathan Thackray <[email protected]> Date: Fri, 17 Oct 2025 01:49:07 +0100 Subject: [PATCH 3/3] fixup! [AArch64][llvm] Armv9.7-A: Add support for GICv5 (FEAT_GCIE) Avoid repetition. PPI and Virtual PPI registers can share code. --- .../Target/AArch64/AArch64SystemOperands.td | 37 ++++++++----------- 1 file changed, 15 insertions(+), 22 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td index 33bbf1a33ba2a..f9af785c542c7 100644 --- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -2520,18 +2520,6 @@ def : RWSysReg<"ICV_HAPR_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b011>; def : RWSysReg<"ICV_HPPIR_EL1", 0b11, 0b000, 0b1100, 0b1010, 0b011>; def : RWSysReg<"ICV_PCR_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b010>; -// PPI Registers -foreach n=0-1 in { - defvar nb = !cast<bit>(n); -// Op0 Op1 CRn CRm Op2 - def : RWSysReg<"ICC_PPI_CACTIVER"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b00,nb}>; - def : RWSysReg<"ICC_PPI_CPENDR"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b10,nb}>; - def : RWSysReg<"ICC_PPI_ENABLER"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1010, {0b11,nb}>; - def : RWSysReg<"ICC_PPI_SACTIVER"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b01,nb}>; - def : RWSysReg<"ICC_PPI_SPENDR"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b11,nb}>; - def : ROSysReg<"ICC_PPI_HMR"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1010, {0b00,nb}>; -} - foreach n=0-3 in { defvar nb = !cast<bits<2>>(n); // Op0 Op1 CRn CRm Op2 @@ -2545,18 +2533,23 @@ foreach n=0-15 in{ def : RWSysReg<"ICC_PPI_PRIORITYR"#n#"_EL1", 0b11, 0b000, 0b1100, {0b111,nb{3}}, nb{2-0}>; } -// Virtual PPI Registers -foreach n=0-1 in { - defvar nb = !cast<bit>(n); -// Op0 Op1 CRn CRm Op2 - def : RWSysReg<"ICV_PPI_CACTIVER"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b00,nb}>; - def : RWSysReg<"ICV_PPI_CPENDR"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b10,nb}>; - def : RWSysReg<"ICV_PPI_ENABLER"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1010, {0b11,nb}>; - def : RWSysReg<"ICV_PPI_SACTIVER"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b01,nb}>; - def : RWSysReg<"ICV_PPI_SPENDR"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b11,nb}>; - def : RWSysReg<"ICV_PPI_HMR"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1010, {0b00,nb}>; +// PPI and Virtual PPI Registers +multiclass PPIRegisters<string prefix> { + foreach n=0-1 in { + defvar nb = !cast<bit>(n); +// Op0 Op1 CRn CRm Op2 + def : RWSysReg<prefix#"_PPI_CACTIVER"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b00,nb}>; + def : RWSysReg<prefix#"_PPI_CPENDR"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b10,nb}>; + def : RWSysReg<prefix#"_PPI_ENABLER"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1010, {0b11,nb}>; + def : RWSysReg<prefix#"_PPI_SACTIVER"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b01,nb}>; + def : RWSysReg<prefix#"_PPI_SPENDR"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b11,nb}>; + def : RWSysReg<prefix#"_PPI_HMR"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1010, {0b00,nb}>; + } } +defm : PPIRegisters<"ICC">; // PPI Registers +defm : PPIRegisters<"ICV">; // Virtual PPI Registers + foreach n=0-15 in { defvar nb = !cast<bits<4>>(n); // Op0 Op1 CRn CRm Op2 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
