https://github.com/jthackray updated https://github.com/llvm/llvm-project/pull/163163
>From 45d71479ab1c15975e7d5068614023327dfcac4d Mon Sep 17 00:00:00 2001 From: Jonathan Thackray <[email protected]> Date: Fri, 5 Sep 2025 23:50:38 +0100 Subject: [PATCH 1/2] [AArch64][llvm] Armv9.7-A: Add support for SVE2p3 shift operations Add instructions for SVE2p3 shift operations: - SQRSHRN - SQRSHRUN - SQSHRN - SQSHRUN - UQRSHRN - UQSHRN as documented here: * https://developer.arm.com/documentation/ddi0602/2025-09/ * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions --- .../lib/Target/AArch64/AArch64SVEInstrInfo.td | 17 +- llvm/lib/Target/AArch64/SVEInstrFormats.td | 22 +- .../MC/AArch64/SVE2p3/qshrn-diagnostics.s | 266 ++++++++++++++++++ llvm/test/MC/AArch64/SVE2p3/qshrn.s | 255 +++++++++++++++++ 4 files changed, 550 insertions(+), 10 deletions(-) create mode 100644 llvm/test/MC/AArch64/SVE2p3/qshrn-diagnostics.s create mode 100644 llvm/test/MC/AArch64/SVE2p3/qshrn.s diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 1d59b1c2abe30..471135a91f432 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -4272,9 +4272,9 @@ def : Pat<(nxv4i32 (partial_reduce_smla nxv4i32:$Acc, nxv8i16:$MulLHS, nxv8i16:$ defm SQCVTN_Z2Z_StoH : sve2p1_multi_vec_extract_narrow<"sqcvtn", 0b00, int_aarch64_sve_sqcvtn_x2>; defm UQCVTN_Z2Z_StoH : sve2p1_multi_vec_extract_narrow<"uqcvtn", 0b01, int_aarch64_sve_uqcvtn_x2>; defm SQCVTUN_Z2Z_StoH : sve2p1_multi_vec_extract_narrow<"sqcvtun", 0b10, int_aarch64_sve_sqcvtun_x2>; -defm SQRSHRN_Z2ZI_StoH : sve2p1_multi_vec_shift_narrow<"sqrshrn", 0b101, int_aarch64_sve_sqrshrn_x2>; -defm UQRSHRN_Z2ZI_StoH : sve2p1_multi_vec_shift_narrow<"uqrshrn", 0b111, int_aarch64_sve_uqrshrn_x2>; -defm SQRSHRUN_Z2ZI_StoH : sve2p1_multi_vec_shift_narrow<"sqrshrun", 0b001, int_aarch64_sve_sqrshrun_x2>; +defm SQRSHRN_Z2ZI_StoH : sve_multi_vec_shift_narrow<"sqrshrn", 0b101, int_aarch64_sve_sqrshrn_x2>; +defm UQRSHRN_Z2ZI_StoH : sve_multi_vec_shift_narrow<"uqrshrn", 0b111, int_aarch64_sve_uqrshrn_x2>; +defm SQRSHRUN_Z2ZI_StoH : sve_multi_vec_shift_narrow<"sqrshrun", 0b001, int_aarch64_sve_sqrshrun_x2>; defm WHILEGE_2PXX : sve2p1_int_while_rr_pair<"whilege", 0b000>; defm WHILEGT_2PXX : sve2p1_int_while_rr_pair<"whilegt", 0b001>; @@ -4648,6 +4648,17 @@ let Predicates = [HasSVE2p3_or_SME2p3] in { defm SCVTFLT_ZZ : sve2_int_to_fp_upcvt<"scvtflt", 0b10>; defm UCVTF_ZZ : sve2_int_to_fp_upcvt<"ucvtf", 0b01>; defm UCVTFLT_ZZ : sve2_int_to_fp_upcvt<"ucvtflt", 0b11>; + + // SVE2 saturating shift right narrow by immediate and interleave + defm SQRSHRN_Z2ZI_HtoB : sve_multi_vec_round_shift_narrow<"sqrshrn", 0b101>; + defm SQRSHRUN_Z2ZI_HtoB : sve_multi_vec_round_shift_narrow<"sqrshrun", 0b001>; + defm SQSHRN_Z2ZI_HtoB : sve_multi_vec_round_shift_narrow<"sqshrn", 0b000>; + defm SQSHRUN_Z2ZI_HtoB : sve_multi_vec_round_shift_narrow<"sqshrun", 0b100>; + defm UQRSHRN_Z2ZI_HtoB : sve_multi_vec_round_shift_narrow<"uqrshrn", 0b111>; + defm UQSHRN_Z2ZI_HtoB : sve_multi_vec_round_shift_narrow<"uqshrn", 0b010>; + defm SQSHRUN_Z2ZI_StoH : sve_multi_vec_shift_narrow<"sqshrun", 0b100, null_frag>; + defm SQSHRN_Z2ZI_StoH : sve_multi_vec_shift_narrow<"sqshrn", 0b000, null_frag>; + defm UQSHRN_Z2ZI_StoH : sve_multi_vec_shift_narrow<"uqshrn", 0b010, null_frag>; } // End HasSME2p3orSVE2p3 //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index ab22d35b8b488..8b9e93f5d324e 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -10050,18 +10050,19 @@ multiclass sve2p1_multi_vec_extract_narrow<string mnemonic, bits<2> opc, SDPatte } // SVE2 multi-vec shift narrow -class sve2p1_multi_vec_shift_narrow<string mnemonic, bits<3> opc, bits<2> tsz> - : I<(outs ZPR16:$Zd), (ins ZZ_s_mul_r:$Zn, vecshiftR16:$imm4), - mnemonic, "\t$Zd, $Zn, $imm4", +class sve2p1_multi_vec_shift_narrow<string mnemonic, ZPRRegOp ZdRC, RegisterOperand ZSrcOp, + Operand immtype, bits<3> opc, bits<2> tsz> + : I<(outs ZdRC:$Zd), (ins ZSrcOp:$Zn, immtype:$imm), + mnemonic, "\t$Zd, $Zn, $imm", "", []>, Sched<[]> { bits<5> Zd; bits<4> Zn; - bits<4> imm4; + bits<4> imm; let Inst{31-23} = 0b010001011; let Inst{22} = tsz{1}; let Inst{21} = 0b1; let Inst{20} = tsz{0}; - let Inst{19-16} = imm4; + let Inst{18-16} = imm{2-0}; // imm3 let Inst{15-14} = 0b00; let Inst{13-11} = opc; let Inst{10} = 0b0; @@ -10072,12 +10073,19 @@ class sve2p1_multi_vec_shift_narrow<string mnemonic, bits<3> opc, bits<2> tsz> let hasSideEffects = 0; } -multiclass sve2p1_multi_vec_shift_narrow<string mnemonic, bits<3> opc, SDPatternOperator intrinsic> { - def NAME : sve2p1_multi_vec_shift_narrow<mnemonic, opc, 0b01>; +multiclass sve_multi_vec_shift_narrow<string mnemonic, bits<3> opc, SDPatternOperator intrinsic> { + def NAME : sve2p1_multi_vec_shift_narrow<mnemonic, ZPR16, ZZ_s_mul_r, vecshiftR16, opc, 0b01> { + let Inst{19} = imm{3}; // imm4 + } def : SVE2p1_Sat_Shift_VG2_Pat<NAME, intrinsic, nxv8i16, nxv4i32, vecshiftR16>; } +multiclass sve_multi_vec_round_shift_narrow<string mnemonic, bits<3> opc> { + def NAME : sve2p1_multi_vec_shift_narrow<mnemonic, ZPR8, ZZ_h_mul_r, vecshiftR8, opc, 0b00> { + let Inst{19} = 0b1; // always 1 for imm3 version + } +} // SME2 multi-vec contiguous load (scalar plus scalar, two registers) class sve2p1_mem_cld_ss_2z<string mnemonic, bits<2> msz, bit n, diff --git a/llvm/test/MC/AArch64/SVE2p3/qshrn-diagnostics.s b/llvm/test/MC/AArch64/SVE2p3/qshrn-diagnostics.s new file mode 100644 index 0000000000000..85add58429237 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p3/qshrn-diagnostics.s @@ -0,0 +1,266 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid element width + +sqrshrn z10.s, { z0.s, z1.s }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrn z10.s, { z0.s, z1.s }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrn z10.d, { z0.d, z1.d }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrn z10.d, { z0.d, z1.d }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid operand for instruction + +sqrshrn z10.h, { z0.b, z1.b }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrshrn z10.h, { z0.b, z1.b }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Intermediate out of range + +sqrshrn z10.b, { z0.h, z1.h }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]. +// CHECK-NEXT: sqrshrn z10.b, { z0.h, z1.h }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrn z10.b, { z0.h, z1.h }, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]. +// CHECK-NEXT: sqrshrn z10.b, { z0.h, z1.h }, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +sqrshrn z10.b, { z0.h, z1.h }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqrshrn z10.b, { z0.h, z1.h }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +sqrshrun z10.s, { z0.s, z1.s }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrun z10.s, { z0.s, z1.s }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrun z10.d, { z0.d, z1.d }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrun z10.d, { z0.d, z1.d }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid operand for instruction + +sqrshrun z10.h, { z0.b, z1.b }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrshrun z10.h, { z0.b, z1.b }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Intermediate out of range + +sqrshrun z10.b, { z0.h, z1.h }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]. +// CHECK-NEXT: sqrshrun z10.b, { z0.h, z1.h }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrun z10.b, { z0.h, z1.h }, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]. +// CHECK-NEXT: sqrshrun z10.b, { z0.h, z1.h }, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +sqrshrun z10.b, { z0.h, z1.h }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqrshrun z10.b, { z0.h, z1.h }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +sqshrn z10.s, { z0.s, z1.s }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshrn z10.s, { z0.s, z1.s }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrn z10.d, { z0.d, z1.d }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshrn z10.d, { z0.d, z1.d }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Intermediate out of range + +sqshrn z10.b, { z0.h, z1.h }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]. +// CHECK-NEXT: sqshrn z10.b, { z0.h, z1.h }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrn z10.b, { z0.h, z1.h }, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]. +// CHECK-NEXT: sqshrn z10.b, { z0.h, z1.h }, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrn z0.h, { z0.s, z1.s }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]. +// CHECK-NEXT: sqshrn z0.h, { z0.s, z1.s }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrn z0.h, { z0.s, z1.s }, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]. +// CHECK-NEXT: sqshrn z0.h, { z0.s, z1.s }, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +sqshrn z10.b, { z0.h, z1.h }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqshrn z10.b, { z0.h, z1.h }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +sqshrun z10.s, { z0.s, z1.s }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshrun z10.s, { z0.s, z1.s }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrun z10.d, { z0.d, z1.d }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshrun z10.d, { z0.d, z1.d }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Intermediate out of range + +sqshrun z10.b, { z0.h, z1.h }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]. +// CHECK-NEXT: sqshrun z10.b, { z0.h, z1.h }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrun z10.b, { z0.h, z1.h }, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]. +// CHECK-NEXT: sqshrun z10.b, { z0.h, z1.h }, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrun z10.h, { z0.s, z1.s }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]. +// CHECK-NEXT: sqshrun z10.h, { z0.s, z1.s }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrun z10.h, { z0.s, z1.s }, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]. +// CHECK-NEXT: sqshrun z10.h, { z0.s, z1.s }, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +sqshrun z10.b, { z0.h, z1.h }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqshrun z10.b, { z0.h, z1.h }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +uqrshrn z10.s, { z0.s, z1.s }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqrshrn z10.s, { z0.s, z1.s }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshrn z10.d, { z0.d, z1.d }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqrshrn z10.d, { z0.d, z1.d }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid operand for instruction + +uqrshrn z10.h, { z0.b, z1.b }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: uqrshrn z10.h, { z0.b, z1.b }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Intermediate out of range + +uqrshrn z10.b, { z0.h, z1.h }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]. +// CHECK-NEXT: uqrshrn z10.b, { z0.h, z1.h }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshrn z10.b, { z0.h, z1.h }, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]. +// CHECK-NEXT: uqrshrn z10.b, { z0.h, z1.h }, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +uqrshrn z10.b, { z0.h, z1.h }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uqrshrn z10.b, { z0.h, z1.h }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +uqshrn z10.s, { z0.s, z1.s }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqshrn z10.s, { z0.s, z1.s }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshrn z10.d, { z0.d, z1.d }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqshrn z10.d, { z0.d, z1.d }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Intermediate out of range + +uqshrn z10.b, { z0.h, z1.h }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]. +// CHECK-NEXT: uqshrn z10.b, { z0.h, z1.h }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshrn z10.b, { z0.h, z1.h }, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]. +// CHECK-NEXT: uqshrn z10.b, { z0.h, z1.h }, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshrn z0.h, { z0.s, z1.s }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]. +// CHECK-NEXT: uqshrn z0.h, { z0.s, z1.s }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshrn z0.h, { z0.s, z1.s }, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]. +// CHECK-NEXT: uqshrn z0.h, { z0.s, z1.s }, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +uqshrn z10.b, { z0.h, z1.h }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uqshrn z10.b, { z0.h, z1.h }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p3/qshrn.s b/llvm/test/MC/AArch64/SVE2p3/qshrn.s new file mode 100644 index 0000000000000..31c87cf342671 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p3/qshrn.s @@ -0,0 +1,255 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p3 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p3 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p3 < %s \ +// RUN: | llvm-objdump -d --mattr=-sve2p3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p3 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p3 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +// ----------------------------------------------------------------- +// Signed saturating rounding shift right narrow by immediate and interleave + +sqrshrn z0.b, { z0.h, z1.h }, #1 +// CHECK-INST: sqrshrn z0.b, { z0.h, z1.h }, #1 +// CHECK-ENCODING: encoding: [0x00,0x28,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af2800 <unknown> + +sqrshrn z31.b, { z30.h, z31.h }, #1 +// CHECK-INST: sqrshrn z31.b, { z30.h, z31.h }, #1 +// CHECK-ENCODING: encoding: [0xdf,0x2b,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af2bdf <unknown> + +sqrshrn z0.b, { z0.h, z1.h }, #8 +// CHECK-INST: sqrshrn z0.b, { z0.h, z1.h }, #8 +// CHECK-ENCODING: encoding: [0x00,0x28,0xa8,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45a82800 <unknown> + +sqrshrn z31.b, { z30.h, z31.h }, #3 +// CHECK-INST: sqrshrn z31.b, { z30.h, z31.h }, #3 +// CHECK-ENCODING: encoding: [0xdf,0x2b,0xad,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45ad2bdf <unknown> + +// ----------------------------------------------------------------- +// Signed saturating rounding shift right unsigned narrow by immediate and interleave + +sqrshrun z0.b, { z0.h, z1.h }, #1 +// CHECK-INST: sqrshrun z0.b, { z0.h, z1.h }, #1 +// CHECK-ENCODING: encoding: [0x00,0x08,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af0800 <unknown> + +sqrshrun z31.b, { z30.h, z31.h }, #1 +// CHECK-INST: sqrshrun z31.b, { z30.h, z31.h }, #1 +// CHECK-ENCODING: encoding: [0xdf,0x0b,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af0bdf <unknown> + +sqrshrun z0.b, { z0.h, z1.h }, #8 +// CHECK-INST: sqrshrun z0.b, { z0.h, z1.h }, #8 +// CHECK-ENCODING: encoding: [0x00,0x08,0xa8,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45a80800 <unknown> + +sqrshrun z31.b, { z30.h, z31.h }, #8 +// CHECK-INST: sqrshrun z31.b, { z30.h, z31.h }, #8 +// CHECK-ENCODING: encoding: [0xdf,0x0b,0xa8,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45a80bdf <unknown> + +// ----------------------------------------------------------------- +// Signed saturating shift right narrow by immediate and interleave + +sqshrn z21.b, { z30.h, z31.h }, #1 +// CHECK-INST: sqshrn z21.b, { z30.h, z31.h }, #1 +// CHECK-ENCODING: encoding: [0xd5,0x03,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af03d5 <unknown> + +sqshrn z31.b, { z30.h, z31.h }, #1 +// CHECK-INST: sqshrn z31.b, { z30.h, z31.h }, #1 +// CHECK-ENCODING: encoding: [0xdf,0x03,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af03df <unknown> + +sqshrn z10.b, { z0.h, z1.h }, #8 +// CHECK-INST: sqshrn z10.b, { z0.h, z1.h }, #8 +// CHECK-ENCODING: encoding: [0x0a,0x00,0xa8,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45a8000a <unknown> + +sqshrn z31.b, { z30.h, z31.h }, #8 +// CHECK-INST: sqshrn z31.b, { z30.h, z31.h }, #8 +// CHECK-ENCODING: encoding: [0xdf,0x03,0xa8,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45a803df <unknown> + +sqshrn z0.b, { z0.h, z1.h }, #1 +// CHECK-INST: sqshrn z0.b, { z0.h, z1.h }, #1 +// CHECK-ENCODING: encoding: [0x00,0x00,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af0000 <unknown> + +sqshrn z0.h, { z0.s, z1.s }, #1 +// CHECK-INST: sqshrn z0.h, { z0.s, z1.s }, #1 +// CHECK-ENCODING: encoding: [0x00,0x00,0xbf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45bf0000 <unknown> + +sqshrn z31.h, { z30.s, z31.s }, #1 +// CHECK-INST: sqshrn z31.h, { z30.s, z31.s }, #1 +// CHECK-ENCODING: encoding: [0xdf,0x03,0xbf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45bf03df <unknown> + +sqshrn z0.h, { z0.s, z1.s }, #16 +// CHECK-INST: sqshrn z0.h, { z0.s, z1.s }, #16 +// CHECK-ENCODING: encoding: [0x00,0x00,0xb0,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45b00000 <unknown> + +sqshrn z31.h, { z30.s, z31.s }, #16 +// CHECK-INST: sqshrn z31.h, { z30.s, z31.s }, #16 +// CHECK-ENCODING: encoding: [0xdf,0x03,0xb0,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45b003df <unknown> + +// ----------------------------------------------------------------- +// Signed saturating shift right unsigned narrow by immediate and interleave + +sqshrun z0.b, { z0.h, z1.h }, #1 +// CHECK-INST: sqshrun z0.b, { z0.h, z1.h }, #1 +// CHECK-ENCODING: encoding: [0x00,0x20,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af2000 <unknown> + +sqshrun z31.b, { z30.h, z31.h }, #1 +// CHECK-INST: sqshrun z31.b, { z30.h, z31.h }, #1 +// CHECK-ENCODING: encoding: [0xdf,0x23,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af23df <unknown> + +sqshrun z0.b, { z0.h, z1.h }, #8 +// CHECK-INST: sqshrun z0.b, { z0.h, z1.h }, #8 +// CHECK-ENCODING: encoding: [0x00,0x20,0xa8,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45a82000 <unknown> + +sqshrun z31.b, { z30.h, z31.h }, #8 +// CHECK-INST: sqshrun z31.b, { z30.h, z31.h }, #8 +// CHECK-ENCODING: encoding: [0xdf,0x23,0xa8,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45a823df <unknown> + +sqshrun z0.h, { z0.s, z1.s }, #1 +// CHECK-INST: sqshrun z0.h, { z0.s, z1.s }, #1 +// CHECK-ENCODING: encoding: [0x00,0x20,0xbf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45bf2000 <unknown> + +sqshrun z31.h, { z30.s, z31.s }, #1 +// CHECK-INST: sqshrun z31.h, { z30.s, z31.s }, #1 +// CHECK-ENCODING: encoding: [0xdf,0x23,0xbf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45bf23df <unknown> + +sqshrun z0.h, { z0.s, z1.s }, #16 +// CHECK-INST: sqshrun z0.h, { z0.s, z1.s }, #16 +// CHECK-ENCODING: encoding: [0x00,0x20,0xb0,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45b02000 <unknown> + +sqshrun z31.h, { z30.s, z31.s }, #16 +// CHECK-INST: sqshrun z31.h, { z30.s, z31.s }, #16 +// CHECK-ENCODING: encoding: [0xdf,0x23,0xb0,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45b023df <unknown> + +// ----------------------------------------------------------------- +// Unsigned saturating rounding shift right narrow by immediate and interleave + +uqrshrn z0.b, { z0.h, z1.h }, #1 +// CHECK-INST: uqrshrn z0.b, { z0.h, z1.h }, #1 +// CHECK-ENCODING: encoding: [0x00,0x38,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af3800 <unknown> + +uqrshrn z31.b, { z30.h, z31.h }, #1 +// CHECK-INST: uqrshrn z31.b, { z30.h, z31.h }, #1 +// CHECK-ENCODING: encoding: [0xdf,0x3b,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af3bdf <unknown> + +uqrshrn z0.b, { z0.h, z1.h }, #8 +// CHECK-INST: uqrshrn z0.b, { z0.h, z1.h }, #8 +// CHECK-ENCODING: encoding: [0x00,0x38,0xa8,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45a83800 <unknown> + +uqrshrn z31.b, { z30.h, z31.h }, #8 +// CHECK-INST: uqrshrn z31.b, { z30.h, z31.h }, #8 +// CHECK-ENCODING: encoding: [0xdf,0x3b,0xa8,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45a83bdf <unknown> + +// ----------------------------------------------------------------- +// Unsigned saturating shift right narrow by immediate and interleave + +uqshrn z0.b, { z0.h, z1.h }, #1 +// CHECK-INST: uqshrn z0.b, { z0.h, z1.h }, #1 +// CHECK-ENCODING: encoding: [0x00,0x10,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af1000 <unknown> + +uqshrn z31.b, { z30.h, z31.h }, #1 +// CHECK-INST: uqshrn z31.b, { z30.h, z31.h }, #1 +// CHECK-ENCODING: encoding: [0xdf,0x13,0xaf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45af13df <unknown> + +uqshrn z0.b, { z0.h, z1.h }, #8 +// CHECK-INST: uqshrn z0.b, { z0.h, z1.h }, #8 +// CHECK-ENCODING: encoding: [0x00,0x10,0xa8,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45a81000 <unknown> + +uqshrn z31.b, { z30.h, z31.h }, #8 +// CHECK-INST: uqshrn z31.b, { z30.h, z31.h }, #8 +// CHECK-ENCODING: encoding: [0xdf,0x13,0xa8,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45a813df <unknown> + +uqshrn z0.h, { z0.s, z1.s }, #1 +// CHECK-INST: uqshrn z0.h, { z0.s, z1.s }, #1 +// CHECK-ENCODING: encoding: [0x00,0x10,0xbf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45bf1000 <unknown> + +uqshrn z31.h, { z30.s, z31.s }, #1 +// CHECK-INST: uqshrn z31.h, { z30.s, z31.s }, #1 +// CHECK-ENCODING: encoding: [0xdf,0x13,0xbf,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45bf13df <unknown> + +uqshrn z0.h, { z0.s, z1.s }, #16 +// CHECK-INST: uqshrn z0.h, { z0.s, z1.s }, #16 +// CHECK-ENCODING: encoding: [0x00,0x10,0xb0,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45b01000 <unknown> + +uqshrn z31.h, { z30.s, z31.s }, #16 +// CHECK-INST: uqshrn z31.h, { z30.s, z31.s }, #16 +// CHECK-ENCODING: encoding: [0xdf,0x13,0xb0,0x45] +// CHECK-ERROR: instruction requires: sme2p3 or sve2p3 +// CHECK-UNKNOWN: 45b013df <unknown> >From 7dbb90be410fc0625dcb419e4e7dd18e2335e050 Mon Sep 17 00:00:00 2001 From: Jonathan Thackray <[email protected]> Date: Thu, 16 Oct 2025 22:44:52 +0100 Subject: [PATCH 2/2] fixup! [AArch64][llvm] Armv9.7-A: Add support for SVE2p3 shift operations Add extra testcases for non-consecutive vectors, and sort out movprfx test --- .../MC/AArch64/SVE2p3/qshrn-diagnostics.s | 53 ++++++++++++++----- 1 file changed, 41 insertions(+), 12 deletions(-) diff --git a/llvm/test/MC/AArch64/SVE2p3/qshrn-diagnostics.s b/llvm/test/MC/AArch64/SVE2p3/qshrn-diagnostics.s index 85add58429237..0a8dc9fb66f88 100644 --- a/llvm/test/MC/AArch64/SVE2p3/qshrn-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE2p3/qshrn-diagnostics.s @@ -34,13 +34,18 @@ sqrshrn z10.b, { z0.h, z1.h }, #9 // CHECK-NEXT: sqrshrn z10.b, { z0.h, z1.h }, #9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: +sqrshrn z10.b, { z1.h, z2.h }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: sqrshrn z10.b, { z1.h, z2.h }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + // --------------------------------------------------------------------------// // Negative tests for instructions that are incompatible with movprfx movprfx z0, z7 -sqrshrn z10.b, { z0.h, z1.h }, #1 +sqrshrn z0.b, { z2.h, z3.h }, #1 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov -// CHECK-NEXT: sqrshrn z10.b, { z0.h, z1.h }, #1 +// CHECK-NEXT: sqrshrn z0.b, { z2.h, z3.h }, #1 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // --------------------------------------------------------------------------// @@ -77,13 +82,18 @@ sqrshrun z10.b, { z0.h, z1.h }, #9 // CHECK-NEXT: sqrshrun z10.b, { z0.h, z1.h }, #9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: +sqrshrun z10.b, { z1.h, z2.h }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: sqrshrun z10.b, { z1.h, z2.h }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + // --------------------------------------------------------------------------// // Negative tests for instructions that are incompatible with movprfx movprfx z0, z7 -sqrshrun z10.b, { z0.h, z1.h }, #1 +sqrshrun z0.b, { z0.h, z1.h }, #1 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov -// CHECK-NEXT: sqrshrun z10.b, { z0.h, z1.h }, #1 +// CHECK-NEXT: sqrshrun z0.b, { z0.h, z1.h }, #1 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // --------------------------------------------------------------------------// @@ -122,14 +132,18 @@ sqshrn z0.h, { z0.s, z1.s }, #17 // CHECK-NEXT: sqshrn z0.h, { z0.s, z1.s }, #17 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: +sqshrn z10.b, { z1.h, z2.h }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: sqshrn z10.b, { z1.h, z2.h }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // --------------------------------------------------------------------------// // Negative tests for instructions that are incompatible with movprfx movprfx z0, z7 -sqshrn z10.b, { z0.h, z1.h }, #1 +sqshrn z0.b, { z0.h, z1.h }, #1 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov -// CHECK-NEXT: sqshrn z10.b, { z0.h, z1.h }, #1 +// CHECK-NEXT: sqshrn z0.b, { z0.h, z1.h }, #1 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // --------------------------------------------------------------------------// @@ -168,13 +182,18 @@ sqshrun z10.h, { z0.s, z1.s }, #17 // CHECK-NEXT: sqshrun z10.h, { z0.s, z1.s }, #17 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: +sqshrun z10.b, { z1.h, z2.h }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: sqshrun z10.b, { z1.h, z2.h }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + // --------------------------------------------------------------------------// // Negative tests for instructions that are incompatible with movprfx movprfx z0, z7 -sqshrun z10.b, { z0.h, z1.h }, #1 +sqshrun z0.b, { z0.h, z1.h }, #1 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov -// CHECK-NEXT: sqshrun z10.b, { z0.h, z1.h }, #1 +// CHECK-NEXT: sqshrun z0.b, { z0.h, z1.h }, #1 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // --------------------------------------------------------------------------// @@ -211,13 +230,18 @@ uqrshrn z10.b, { z0.h, z1.h }, #9 // CHECK-NEXT: uqrshrn z10.b, { z0.h, z1.h }, #9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: +uqrshrn z10.b, { z1.h, z2.h }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: uqrshrn z10.b, { z1.h, z2.h }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + // --------------------------------------------------------------------------// // Negative tests for instructions that are incompatible with movprfx movprfx z0, z7 -uqrshrn z10.b, { z0.h, z1.h }, #1 +uqrshrn z0.b, { z0.h, z1.h }, #1 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov -// CHECK-NEXT: uqrshrn z10.b, { z0.h, z1.h }, #1 +// CHECK-NEXT: uqrshrn z0.b, { z0.h, z1.h }, #1 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // --------------------------------------------------------------------------// @@ -256,11 +280,16 @@ uqshrn z0.h, { z0.s, z1.s }, #17 // CHECK-NEXT: uqshrn z0.h, { z0.s, z1.s }, #17 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: +uqshrn z10.b, { z1.h, z2.h }, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: uqshrn z10.b, { z1.h, z2.h }, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + // --------------------------------------------------------------------------// // Negative tests for instructions that are incompatible with movprfx movprfx z0, z7 -uqshrn z10.b, { z0.h, z1.h }, #1 +uqshrn z0.b, { z0.h, z1.h }, #1 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov -// CHECK-NEXT: uqshrn z10.b, { z0.h, z1.h }, #1 +// CHECK-NEXT: uqshrn z0.b, { z0.h, z1.h }, #1 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
