https://github.com/lei137 created https://github.com/llvm/llvm-project/pull/161572
None >From ea6d743c7a6c572053b360fc4eee2dedad681b21 Mon Sep 17 00:00:00 2001 From: Lei Huang <[email protected]> Date: Tue, 30 Sep 2025 18:09:31 +0000 Subject: [PATCH] [PowerPC] Implement paddis --- .../Target/PowerPC/AsmParser/PPCAsmParser.cpp | 7 +++ .../PowerPC/MCTargetDesc/PPCAsmBackend.cpp | 9 ++++ .../PowerPC/MCTargetDesc/PPCFixupKinds.h | 6 +++ .../PowerPC/MCTargetDesc/PPCInstPrinter.cpp | 12 +++++ .../PowerPC/MCTargetDesc/PPCInstPrinter.h | 2 + .../PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp | 1 + llvm/lib/Target/PowerPC/PPCInstrFuture.td | 44 +++++++++++++++++++ llvm/lib/Target/PowerPC/PPCRegisterInfo.td | 19 ++++++++ .../PowerPC/ppc-encoding-ISAFuture.txt | 6 +++ .../PowerPC/ppc64le-encoding-ISAFuture.txt | 6 +++ llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s | 8 ++++ 11 files changed, 120 insertions(+) diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp index 1fc475dc6cb7e..d09bd9d38d585 100644 --- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp +++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp @@ -388,6 +388,13 @@ struct PPCOperand : public MCParsedAsmOperand { return Kind == Expression || (Kind == Immediate && isInt<34>(getImm()) && (getImm() & 15) == 0); } + + bool isS32Imm() const { + // Once the PC-Rel ABI is finalized, evaluate whether a 32-bit + // ContextImmediate is needed. + return Kind == Expression || (Kind == Immediate && isInt<32>(getImm())); + } + bool isS34Imm() const { // Once the PC-Rel ABI is finalized, evaluate whether a 34-bit // ContextImmediate is needed. diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp index 04b886ae74993..558351b515a2e 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp @@ -47,6 +47,9 @@ static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) { case PPC::fixup_ppc_half16ds: case PPC::fixup_ppc_half16dq: return Value & 0xfffc; + case PPC::fixup_ppc_pcrel32: + case PPC::fixup_ppc_imm32: + return Value & 0xffffffff; case PPC::fixup_ppc_pcrel34: case PPC::fixup_ppc_imm34: return Value & 0x3ffffffff; @@ -71,6 +74,8 @@ static unsigned getFixupKindNumBytes(unsigned Kind) { case PPC::fixup_ppc_br24abs: case PPC::fixup_ppc_br24_notoc: return 4; + case PPC::fixup_ppc_pcrel32: + case PPC::fixup_ppc_imm32: case PPC::fixup_ppc_pcrel34: case PPC::fixup_ppc_imm34: case FK_Data_8: @@ -154,6 +159,8 @@ MCFixupKindInfo PPCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { {"fixup_ppc_brcond14abs", 16, 14, 0}, {"fixup_ppc_half16", 0, 16, 0}, {"fixup_ppc_half16ds", 0, 14, 0}, + {"fixup_ppc_pcrel32", 0, 32, 0}, + {"fixup_ppc_imm32", 0, 32, 0}, {"fixup_ppc_pcrel34", 0, 34, 0}, {"fixup_ppc_imm34", 0, 34, 0}, {"fixup_ppc_nofixup", 0, 0, 0}}; @@ -166,6 +173,8 @@ MCFixupKindInfo PPCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { {"fixup_ppc_brcond14abs", 2, 14, 0}, {"fixup_ppc_half16", 0, 16, 0}, {"fixup_ppc_half16ds", 2, 14, 0}, + {"fixup_ppc_pcrel32", 0, 32, 0}, + {"fixup_ppc_imm32", 0, 32, 0}, {"fixup_ppc_pcrel34", 0, 34, 0}, {"fixup_ppc_imm34", 0, 34, 0}, {"fixup_ppc_nofixup", 0, 0, 0}}; diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h index df0c666f5b113..4164b697649cd 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h @@ -40,6 +40,12 @@ enum Fixups { /// instrs like 'std'. fixup_ppc_half16ds, + // A 32-bit fixup corresponding to PC-relative paddis. + fixup_ppc_pcrel32, + + // A 32-bit fixup corresponding to Non-PC-relative paddis. + fixup_ppc_imm32, + // A 34-bit fixup corresponding to PC-relative paddi. fixup_ppc_pcrel34, diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp index b27bc3bd49315..e2afb9378cbf0 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp @@ -430,6 +430,18 @@ void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo, printOperand(MI, OpNo, STI, O); } +void PPCInstPrinter::printS32ImmOperand(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O) { + if (MI->getOperand(OpNo).isImm()) { + long long Value = MI->getOperand(OpNo).getImm(); + assert(isInt<32>(Value) && "Invalid s32imm argument!"); + O << (long long)Value; + } + else + printOperand(MI, OpNo, STI, O); +} + void PPCInstPrinter::printS34ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h index 48f66ca26958e..69d39d4e410bf 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h @@ -80,6 +80,8 @@ class PPCInstPrinter : public MCInstPrinter { const MCSubtargetInfo &STI, raw_ostream &O); void printS16ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); + void printS32ImmOperand(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, raw_ostream &O); void printS34ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printU16ImmOperand(const MCInst *MI, unsigned OpNo, diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp index a8e00198d7f41..9d125233cb19a 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp @@ -46,6 +46,7 @@ static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset, case PPC::fixup_ppc_br24_notoc: case PPC::fixup_ppc_brcond14: case PPC::fixup_ppc_pcrel34: + case PPC::fixup_ppc_pcrel32: PCRel = true; } Fixups.push_back(MCFixup::create(Offset, Value, Kind, PCRel)); diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td index 1aefea1a1c498..8a80a95b531aa 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td +++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td @@ -284,9 +284,41 @@ class 8RR_XX4Form_XTABC6_P<bits<6> opcode, dag OOL, dag IOL, string asmstr, let Inst{63} = XT{5}; } +class MLS_DForm_R_SI32_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : PI<1, opcode, OOL, IOL, asmstr, itin> { + bits<5> RT; + bits<5> RA; + bits<32> SI; + + let Pattern = pattern; + + // The prefix. + let Inst{6...7} = 2; + let Inst{8} = 0; + let Inst{11} = PCRel; + let Inst{16...31} = SI{31...16}; + + // The instruction. + let Inst{38...42} = RT; + let Inst{43...47} = RA; + let Inst{48...63} = SI{15...0}; +} + +multiclass MLS_DForm_R_SI32_RTA5_p<bits<6> opcode, dag OOL, dag IOL, + dag PCRel_IOL, string asmstr, + InstrItinClass itin> { + def NAME : MLS_DForm_R_SI32_RTA5<opcode, OOL, IOL, !strconcat(asmstr, ", 0"), + itin, []>; + def pc : MLS_DForm_R_SI32_RTA5<opcode, OOL, PCRel_IOL, + !strconcat(asmstr, ", 1"), itin, []>, + isPCRel; +} + //-------------------------- Instruction definitions -------------------------// // Predicate combinations available: // [IsISAFuture] +// [IsISAFuture, PrefixInstrs] // [HasVSX, IsISAFuture] // [HasVSX, PrefixInstrs, IsISAFuture] @@ -296,6 +328,18 @@ let Predicates = [IsISAFuture] in { "$RT, $L, $RA, $RB", []>; } +let Predicates = [IsISAFuture, PrefixInstrs] in { + defm PADDIS : MLS_DForm_R_SI32_RTA5_p<15, (outs gprc:$RT), + (ins gprc_nor0:$RA, s32imm:$SI), + (ins immZero:$RA, s32imm_pcrel:$SI), + "paddis $RT, $RA, $SI", IIC_LdStLFD>; + let Interpretation64Bit = 1, isCodeGenOnly = 1 in + defm PADDIS8 : MLS_DForm_R_SI32_RTA5_p<15, (outs g8rc:$RT), + (ins g8rc_nox0:$RA, s32imm:$SI), + (ins immZero:$RA, s32imm_pcrel:$SI), + "paddis $RT, $RA, $SI", IIC_LdStLFD>; +} + let Predicates = [HasVSX, IsISAFuture] in { let mayLoad = 1 in { def LXVRL : XX1Form_memOp<31, 525, (outs vsrc:$XT), diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td index 74333c57244e7..77912a2c06213 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td @@ -797,6 +797,25 @@ def s17imm64 : Operand<i64> { let DecoderMethod = "decodeSImmOperand<16>"; let OperandType = "OPERAND_IMMEDIATE"; } +def PPCS32ImmAsmOperand : AsmOperandClass { + let Name = "S32Imm"; + let PredicateMethod = "isS32Imm"; + let RenderMethod = "addImmOperands"; +} +def s32imm : Operand<i64> { + let PrintMethod = "printS32ImmOperand"; + let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_imm32>"; + let ParserMatchClass = PPCS32ImmAsmOperand; + let DecoderMethod = "decodeSImmOperand<32>"; + let OperandType = "OPERAND_IMMEDIATE"; +} +def s32imm_pcrel : Operand<i64> { + let PrintMethod = "printS32ImmOperand"; + let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_pcrel32>"; + let ParserMatchClass = PPCS32ImmAsmOperand; + let DecoderMethod = "decodeSImmOperand<32>"; + let OperandType = "OPERAND_IMMEDIATE"; +} def PPCS34ImmAsmOperand : AsmOperandClass { let Name = "S34Imm"; let PredicateMethod = "isS34Imm"; diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt index cdfc8ce9e0ca5..bdbfdae6ce944 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt @@ -274,6 +274,12 @@ #CHECK: xvmulhuh 4, 5, 7 0xf0,0x85,0x3b,0xd0 +#CHECK: paddis 10, 12, 1000000000, 0 +0x06,0x00,0x3b,0x9a,0x3d,0x4c,0xca,0x00 + +#CHECK: paddis 10, 0, 1000000000, 1 +0x06,0x10,0x3b,0x9a,0x3d,0x40,0xca,0x00 + #CHECK: xxmulmul 8, 3, 4, 2 0xed,0x03,0x22,0x08 diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt index f7e314fc819e4..996ffc6fe4a21 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt @@ -268,6 +268,12 @@ #CHECK: xvmulhuh 4, 5, 7 0xd0,0x3b,0x85,0xf0 +#CHECK: paddis 10, 12, 1000000000, 0 +0x9a,0x3b,0x00,0x06,0x00,0xca,0x4c,0x3d + +#CHECK: paddis 10, 0, 1000000000, 1 +0x9a,0x3b,0x10,0x06,0x00,0xca,0x40,0x3d + #CHECK: xxmulmul 8, 3, 4, 2 0x08,0x22,0x03,0xed diff --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s index 29fedd7c20646..f7023e65e35f9 100644 --- a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s +++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s @@ -387,6 +387,14 @@ #CHECK-BE: xvmulhuh 4, 5, 7 # encoding: [0xf0,0x85,0x3b,0xd0] #CHECK-LE: xvmulhuh 4, 5, 7 # encoding: [0xd0,0x3b,0x85,0xf0] + paddis 10, 12, 1000000000, 0 +#CHECK-BE: paddis 10, 12, 1000000000, 0 # encoding: [0x06,0x00,0x3b,0x9a, +#CHECK-BE-SAME: 0x3d,0x4c,0xca,0x00] + + paddis 10, 0, 1000000000, 1 +#CHECK-BE: paddis 10, 0, 1000000000, 1 # encoding: [0x06,0x10,0x3b,0x9a, +#CHECK-BE-SAME: 0x3d,0x40,0xca,0x00] + xxmulmul 8, 3, 4, 2 #CHECK-BE: xxmulmul 8, 3, 4, 2 # encoding: [0xed,0x03,0x22,0x08] #CHECK-LE: xxmulmul 8, 3, 4, 2 # encoding: [0x08,0x22,0x03,0xed] _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
