https://github.com/jthackray updated https://github.com/llvm/llvm-project/pull/163158
>From 8f4b9402a913845e3fb0c2b4f94dc6336170db0c Mon Sep 17 00:00:00 2001 From: Jonathan Thackray <[email protected]> Date: Fri, 5 Sep 2025 23:09:56 +0100 Subject: [PATCH 1/4] [AArch64][llvm] Armv9.7-A: Add support for Virtual Memory Tagging (FEAT_MTETC) Add the following instructions for `FEAT_MTETC`, which is a part of `FEAT_VMTE` for Virtual Tagging: * `DC ZGBVA` * `DC GBVA` as documented here: * https://developer.arm.com/documentation/ddi0602/2025-09/ * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions --- clang/test/Driver/aarch64-v97a.c | 4 +++ .../print-supported-extensions-aarch64.c | 1 + llvm/lib/Target/AArch64/AArch64Features.td | 3 ++ llvm/lib/Target/AArch64/AArch64InstrInfo.td | 2 ++ .../Target/AArch64/AArch64SystemOperands.td | 6 ++++ .../AArch64/AsmParser/AArch64AsmParser.cpp | 1 + llvm/test/MC/AArch64/arm-mtetc.s | 29 +++++++++++++++++++ .../TargetParser/TargetParserTest.cpp | 4 ++- 8 files changed, 49 insertions(+), 1 deletion(-) create mode 100644 llvm/test/MC/AArch64/arm-mtetc.s diff --git a/clang/test/Driver/aarch64-v97a.c b/clang/test/Driver/aarch64-v97a.c index 9d9e946df6f65..3c6ca22481d97 100644 --- a/clang/test/Driver/aarch64-v97a.c +++ b/clang/test/Driver/aarch64-v97a.c @@ -33,3 +33,7 @@ // RUN: %clang -target aarch64 -march=armv9.7a+mpamv2 -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MPAMv2 %s // RUN: %clang -target aarch64 -march=armv9.7-a+mpamv2 -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MPAMv2 %s // V97A-MPAMv2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+mpamv2" + +// RUN: %clang -target aarch64 -march=armv9.7a+mtetc -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-MTETC %s +// RUN: %clang -target aarch64 -march=armv9.7-a+mtetc -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-MTETC %s +// VFAT-MTETC: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+mtetc" diff --git a/clang/test/Driver/print-supported-extensions-aarch64.c b/clang/test/Driver/print-supported-extensions-aarch64.c index 6a6f4e03e4f83..05ecc0dd8ec89 100644 --- a/clang/test/Driver/print-supported-extensions-aarch64.c +++ b/clang/test/Driver/print-supported-extensions-aarch64.c @@ -47,6 +47,7 @@ // CHECK-NEXT: mops FEAT_MOPS Enable Armv8.8-A memcpy and memset acceleration instructions // CHECK-NEXT: mpamv2 FEAT_MPAMv2 Enable Armv9.7-A MPAMv2 Lookaside Buffer Invalidate instructions // CHECK-NEXT: memtag FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension +// CHECK-NEXT: mtetc FEAT_MTETC Enable Virtual Memory Tagging Extension // CHECK-NEXT: simd FEAT_AdvSIMD Enable Advanced SIMD instructions // CHECK-NEXT: occmo FEAT_OCCMO Enable Armv9.6-A Outer cacheable cache maintenance operations // CHECK-NEXT: pauth FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td index b277d1d2e9453..d0b7ed34d0309 100644 --- a/llvm/lib/Target/AArch64/AArch64Features.td +++ b/llvm/lib/Target/AArch64/AArch64Features.td @@ -601,6 +601,9 @@ def FeatureTLBID: ExtensionWithMArch<"tlbid", "TLBID", "FEAT_TLBID", def FeatureMPAMv2: ExtensionWithMArch<"mpamv2", "MPAMv2", "FEAT_MPAMv2", "Enable Armv9.7-A MPAMv2 Lookaside Buffer Invalidate instructions">; +def FeatureMTETC: ExtensionWithMArch<"mtetc", "MTETC", "FEAT_MTETC", + "Enable Virtual Memory Tagging Extension">; + //===----------------------------------------------------------------------===// // Other Features //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 483db5dd28d72..390f91a89af9f 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -404,6 +404,8 @@ def HasTLBID : Predicate<"Subtarget->hasTLBID()">, AssemblerPredicateWithAll<(all_of FeatureTLBID), "tlbid">; def HasMPAMv2 : Predicate<"Subtarget->hasMPAMv2()">, AssemblerPredicateWithAll<(all_of FeatureMPAMv2), "mpamv2">; +def HasMTETC : Predicate<"Subtarget->hasMTETC()">, + AssemblerPredicateWithAll<(all_of FeatureMTETC), "mtetc">; def IsLE : Predicate<"Subtarget->isLittleEndian()">; def IsBE : Predicate<"!Subtarget->isLittleEndian()">; def IsWindows : Predicate<"Subtarget->isTargetWindows()">; diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td index 163e172fca1b1..db560f0786a3e 100644 --- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -205,6 +205,7 @@ def lookupDCByName : SearchIndex { let Key = ["Name"]; } +// Op1 CRn CRm Op2 def : DC<"ZVA", 0b011, 0b0111, 0b0100, 0b001>; def : DC<"IVAC", 0b000, 0b0111, 0b0110, 0b001>; def : DC<"ISW", 0b000, 0b0111, 0b0110, 0b010>; @@ -241,6 +242,11 @@ def : DC<"CIGDVAC", 0b011, 0b0111, 0b1110, 0b101>; def : DC<"GZVA", 0b011, 0b0111, 0b0100, 0b100>; } +let Requires = [{ {AArch64::FeatureMTETC} }] in { +def : DC<"ZGBVA", 0b011, 0b0111, 0b0100, 0b101>; +def : DC<"GBVA", 0b011, 0b0111, 0b0100, 0b111>; +} + let Requires = [{ {AArch64::FeatureMEC} }] in { def : DC<"CIPAE", 0b100, 0b0111, 0b1110, 0b000>; def : DC<"CIGDPAE", 0b100, 0b0111, 0b1110, 0b111>; diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 950d55de8fa59..e8e2f3c2ecd7e 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -3887,6 +3887,7 @@ static const struct Extension { {"lscp", {AArch64::FeatureLSCP}}, {"tlbid", {AArch64::FeatureTLBID}}, {"mpamv2", {AArch64::FeatureMPAMv2}}, + {"mtetc", {AArch64::FeatureMTETC}}, }; static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) { diff --git a/llvm/test/MC/AArch64/arm-mtetc.s b/llvm/test/MC/AArch64/arm-mtetc.s new file mode 100644 index 0000000000000..8483e7612fc61 --- /dev/null +++ b/llvm/test/MC/AArch64/arm-mtetc.s @@ -0,0 +1,29 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mtetc < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+all < %s \ +// RUN: | llvm-objdump -d --mattr=+mtetc --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+all < %s \ +// RUN: | llvm-objdump -d --mattr=-mtetc --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mtetc < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+mtetc -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +//------------------------------------------------------------------------------ +// FEAT_MTETC Extension instructions +//------------------------------------------------------------------------------ + +dc zgbva, x0 +// CHECK-INST: dc zgbva, x0 +// CHECK-ENCODING: [0xa0,0x74,0x0b,0xd5] +// CHECK-UNKNOWN: d50b74a0 sys #3, c7, c4, #5, x0 +// CHECK-ERROR: DC ZGBVA requires: mtetc + +dc gbva, x0 +// CHECK-INST: dc gbva, x0 +// CHECK-ENCODING: [0xe0,0x74,0x0b,0xd5] +// CHECK-UNKNOWN: d50b74e0 sys #3, c7, c4, #7, x0 +// CHECK-ERROR: DC GBVA requires: mtetc diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index b489536ea5b94..fdf937fa8cfdc 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1445,7 +1445,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) { AArch64::AEK_SSVE_BITPERM, AArch64::AEK_SVESHA3, AArch64::AEK_SVESM4, AArch64::AEK_CMH, AArch64::AEK_LSCP, AArch64::AEK_TLBID, - AArch64::AEK_MPAMV2, + AArch64::AEK_MPAMV2, AArch64::AEK_MTETC, }; std::vector<StringRef> Features; @@ -1561,6 +1561,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) { EXPECT_TRUE(llvm::is_contained(Features, "+lscp")); EXPECT_TRUE(llvm::is_contained(Features, "+tlbid")); EXPECT_TRUE(llvm::is_contained(Features, "+mpamv2")); + EXPECT_TRUE(llvm::is_contained(Features, "+mtetc")); // Assuming we listed every extension above, this should produce the same // result. @@ -1731,6 +1732,7 @@ TEST(TargetParserTest, AArch64ArchExtFeature) { {"lscp", "nolscp", "+lscp", "-lscp"}, {"tlbid", "notlbid", "+tlbid", "-tlbid"}, {"mpamv2", "nompamv2", "+mpamv2", "-mpamv2"}, + {"mtetc", "nomtetc", "+mtetc", "-mtetc"}, }; for (unsigned i = 0; i < std::size(ArchExt); i++) { >From 60a54c0f2a741f33366b458347b6917b17e3007d Mon Sep 17 00:00:00 2001 From: Jonathan Thackray <[email protected]> Date: Mon, 13 Oct 2025 18:57:38 +0100 Subject: [PATCH 2/4] fixup! [AArch64][llvm] Armv9.7-A: Add support for Virtual Memory Tagging (FEAT_MTETC) FEAT_MTETC is now part of Armv9.7-A, so fix prefix --- clang/test/Driver/aarch64-v97a.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/clang/test/Driver/aarch64-v97a.c b/clang/test/Driver/aarch64-v97a.c index 3c6ca22481d97..5f2631701ba4c 100644 --- a/clang/test/Driver/aarch64-v97a.c +++ b/clang/test/Driver/aarch64-v97a.c @@ -34,6 +34,6 @@ // RUN: %clang -target aarch64 -march=armv9.7-a+mpamv2 -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MPAMv2 %s // V97A-MPAMv2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+mpamv2" -// RUN: %clang -target aarch64 -march=armv9.7a+mtetc -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-MTETC %s -// RUN: %clang -target aarch64 -march=armv9.7-a+mtetc -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-MTETC %s -// VFAT-MTETC: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+mtetc" +// RUN: %clang -target aarch64 -march=armv9.7a+mtetc -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MTETC %s +// RUN: %clang -target aarch64 -march=armv9.7-a+mtetc -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MTETC %s +// V97A-MTETC: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+mtetc" >From f1568d44450835130045fee43c2c2e8f68d44842 Mon Sep 17 00:00:00 2001 From: Jonathan Thackray <[email protected]> Date: Thu, 16 Oct 2025 11:56:54 +0100 Subject: [PATCH 3/4] fixup! [AArch64][llvm] Armv9.7-A: Add support for Virtual Memory Tagging (FEAT_MTETC) Add llvm/test/MC/AArch64/armv9.7a-mtetc-diagnostics.s --- .../test/MC/AArch64/armv9.7a-mtetc-diagnostics.s | 16 ++++++++++++++++ .../MC/AArch64/{arm-mtetc.s => armv9.7a-mtetc.s} | 0 2 files changed, 16 insertions(+) create mode 100644 llvm/test/MC/AArch64/armv9.7a-mtetc-diagnostics.s rename llvm/test/MC/AArch64/{arm-mtetc.s => armv9.7a-mtetc.s} (100%) diff --git a/llvm/test/MC/AArch64/armv9.7a-mtetc-diagnostics.s b/llvm/test/MC/AArch64/armv9.7a-mtetc-diagnostics.s new file mode 100644 index 0000000000000..dc2a2905709e2 --- /dev/null +++ b/llvm/test/MC/AArch64/armv9.7a-mtetc-diagnostics.s @@ -0,0 +1,16 @@ +// RUN: not llvm-mc -triple=aarch64 -mattr=+mtetc -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-REQUIRES-MTETC + +//------------------------------------------------------------------------------ +// FEAT_MTETC Extension instructions +//------------------------------------------------------------------------------ + +dc zgbva +// CHECK-ERROR: error: specified dc op requires a register +// CHECK-REQUIRES-MTETC: DC ZGBVA requires: mtetc + +dc gbva +// CHECK-ERROR: error: specified dc op requires a register +// CHECK-REQUIRES-MTETC: DC GBVA requires: mtetc diff --git a/llvm/test/MC/AArch64/arm-mtetc.s b/llvm/test/MC/AArch64/armv9.7a-mtetc.s similarity index 100% rename from llvm/test/MC/AArch64/arm-mtetc.s rename to llvm/test/MC/AArch64/armv9.7a-mtetc.s >From 2ec928f4ddc677db1fc882e7a214ef21949367e5 Mon Sep 17 00:00:00 2001 From: Jonathan Thackray <[email protected]> Date: Wed, 22 Oct 2025 16:19:14 +0100 Subject: [PATCH 4/4] fixup! [AArch64][llvm] Armv9.7-A: Add support for Virtual Memory Tagging (FEAT_MTETC) s/-mattr=+all/-mattr=+mtetc/ in test file --- llvm/test/MC/AArch64/armv9.7a-mtetc.s | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/test/MC/AArch64/armv9.7a-mtetc.s b/llvm/test/MC/AArch64/armv9.7a-mtetc.s index 8483e7612fc61..087b23b8f1478 100644 --- a/llvm/test/MC/AArch64/armv9.7a-mtetc.s +++ b/llvm/test/MC/AArch64/armv9.7a-mtetc.s @@ -2,9 +2,9 @@ // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ // RUN: | FileCheck %s --check-prefix=CHECK-ERROR -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+all < %s \ +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+mtetc < %s \ // RUN: | llvm-objdump -d --mattr=+mtetc --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+all < %s \ +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+mtetc < %s \ // RUN: | llvm-objdump -d --mattr=-mtetc --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN // Disassemble encoding and check the re-encoding (-show-encoding) matches. // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mtetc < %s \ _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
