llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-systemz Author: Nicolai Hähnle (nhaehnle) <details> <summary>Changes</summary> There can only be meaningful aliasing between the memory accesses of different instructions if at least one of the accesses modifies memory. This check is applied at the instruction-level earlier in the method. This change merely extends the check on a per-MMO basis. This affects a SystemZ test because PFD instructions are both mayLoad and mayStore but may carry a load-only MMO which is now no longer treated as aliasing loads. The PFD instructions are from llvm.prefetch generated by loop-data-prefetch. --- **Stack**: - [5/5] #<!-- -->166213 - [4/5] #<!-- -->166212 - [3/5] #<!-- -->166211 ⬅ - [2/5] #<!-- -->166210 - [1/5] #<!-- -->166209 ⚠️ *Part of a stack created by [spr](https://github.com/ejoffe/spr). Merging this PR using the GitHub UI may have unexpected results.* --- Full diff: https://github.com/llvm/llvm-project/pull/166211.diff 2 Files Affected: - (modified) llvm/lib/CodeGen/MachineInstr.cpp (+6-2) - (modified) llvm/test/CodeGen/SystemZ/vec-load-element.ll (+2-2) ``````````diff diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index 8ad9245a47684..37e5c517d24d8 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -1547,10 +1547,14 @@ bool MachineInstr::mayAlias(BatchAAResults *AA, const MachineInstr &Other, // Check each pair of memory operands from both instructions, which can't // alias only if all pairs won't alias. - for (auto *MMOa : memoperands()) - for (auto *MMOb : Other.memoperands()) + for (auto *MMOa : memoperands()) { + for (auto *MMOb : Other.memoperands()) { + if (!MMOa->isStore() && !MMOb->isStore()) + continue; if (MemOperandsHaveAlias(MFI, AA, UseTBAA, MMOa, MMOb)) return true; + } + } return false; } diff --git a/llvm/test/CodeGen/SystemZ/vec-load-element.ll b/llvm/test/CodeGen/SystemZ/vec-load-element.ll index 2baaed19546df..9bef279d7c0fa 100644 --- a/llvm/test/CodeGen/SystemZ/vec-load-element.ll +++ b/llvm/test/CodeGen/SystemZ/vec-load-element.ll @@ -5,8 +5,8 @@ ; CHECK-LABEL: .LBB0_1: ; CHECK-NOT: l %r ; CHECK-NOT: vlvgf -; CHECK: pfd -; CHECK: vlef +; CHECK-DAG: pfd +; CHECK-DAG: vlef %type0 = type { i32, [400 x i8], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } @Mem = external global [150 x %type0], align 4 `````````` </details> https://github.com/llvm/llvm-project/pull/166211 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
