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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
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<details>
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``````````bash
git-clang-format --diff origin/main HEAD --extensions h,cpp --
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64MCInstLower.cpp --diff_from_common_commit
``````````
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``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index a86aac88b..54d0ea168 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -511,7 +511,7 @@ AArch64TargetLowering::AArch64TargetLowering(const
TargetMachine &TM,
setOperationAction(ISD::BR_CC, MVT::f64, Custom);
setOperationAction(ISD::SELECT, MVT::i32, Custom);
setOperationAction(ISD::SELECT, MVT::i64, Custom);
- setOperationAction(ISD::CTSELECT, MVT::i8, Promote);
+ setOperationAction(ISD::CTSELECT, MVT::i8, Promote);
setOperationAction(ISD::CTSELECT, MVT::i16, Promote);
setOperationAction(ISD::CTSELECT, MVT::i32, Custom);
setOperationAction(ISD::CTSELECT, MVT::i64, Custom);
@@ -534,7 +534,8 @@ AArch64TargetLowering::AArch64TargetLowering(const
TargetMachine &TM,
MVT elemType = VT.getVectorElementType();
if (elemType == MVT::i8 || elemType == MVT::i16) {
setOperationAction(ISD::CTSELECT, VT, Promote);
- } else if ((elemType == MVT::f16 || elemType == MVT::bf16) &&
!Subtarget->hasFullFP16()) {
+ } else if ((elemType == MVT::f16 || elemType == MVT::bf16) &&
+ !Subtarget->hasFullFP16()) {
setOperationAction(ISD::CTSELECT, VT, Promote);
} else {
setOperationAction(ISD::CTSELECT, VT, Expand);
@@ -3351,7 +3352,9 @@ void AArch64TargetLowering::fixupPtrauthDiscriminator(
IntDiscOp.setImm(IntDisc);
}
-MachineBasicBlock *AArch64TargetLowering::EmitCTSELECT(MachineInstr &MI,
MachineBasicBlock *MBB, unsigned Opcode) const {
+MachineBasicBlock *AArch64TargetLowering::EmitCTSELECT(MachineInstr &MI,
+ MachineBasicBlock *MBB,
+ unsigned Opcode) const {
const TargetInstrInfo *TII = Subtarget->getInstrInfo();
DebugLoc DL = MI.getDebugLoc();
MachineInstrBuilder Builder = BuildMI(*MBB, MI, DL, TII->get(Opcode));
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index d14d64ffe..987377bc4 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -207,7 +207,8 @@ public:
MachineOperand &AddrDiscOp,
const TargetRegisterClass *AddrDiscRC) const;
- MachineBasicBlock *EmitCTSELECT(MachineInstr &MI, MachineBasicBlock *BB,
unsigned Opcode) const;
+ MachineBasicBlock *EmitCTSELECT(MachineInstr &MI, MachineBasicBlock *BB,
+ unsigned Opcode) const;
MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr &MI,
@@ -928,9 +929,7 @@ private:
return VT.isScalableVector();
}
- bool isSelectSupported(SelectSupportKind Kind) const override {
- return true;
- }
+ bool isSelectSupported(SelectSupportKind Kind) const override { return true;
}
};
namespace AArch64 {
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 227e5d596..bab67f57e 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -2113,7 +2113,8 @@ bool AArch64InstrInfo::removeCmpToZeroOrOne(
return true;
}
-static inline void expandCtSelect(MachineBasicBlock &MBB, MachineInstr &MI,
DebugLoc &DL, const MCInstrDesc &MCID) {
+static inline void expandCtSelect(MachineBasicBlock &MBB, MachineInstr &MI,
+ DebugLoc &DL, const MCInstrDesc &MCID) {
MachineInstrBuilder Builder = BuildMI(MBB, MI, DL, MCID);
for (unsigned Idx = 0; Idx < MI.getNumOperands(); ++Idx) {
Builder.add(MI.getOperand(Idx));
@@ -2129,24 +2130,24 @@ bool AArch64InstrInfo::expandPostRAPseudo(MachineInstr
&MI) const {
DebugLoc DL = MI.getDebugLoc();
switch (MI.getOpcode()) {
- case AArch64::I32CTSELECT:
- expandCtSelect(MBB, MI, DL, get(AArch64::CSELWr));
- return true;
- case AArch64::I64CTSELECT:
- expandCtSelect(MBB, MI, DL, get(AArch64::CSELXr));
- return true;
- case AArch64::BF16CTSELECT:
- expandCtSelect(MBB, MI, DL, get(AArch64::FCSELHrrr));
- return true;
- case AArch64::F16CTSELECT:
- expandCtSelect(MBB, MI, DL, get(AArch64::FCSELHrrr));
- return true;
- case AArch64::F32CTSELECT:
- expandCtSelect(MBB, MI, DL, get(AArch64::FCSELSrrr));
- return true;
- case AArch64::F64CTSELECT:
- expandCtSelect(MBB, MI, DL, get(AArch64::FCSELDrrr));
- return true;
+ case AArch64::I32CTSELECT:
+ expandCtSelect(MBB, MI, DL, get(AArch64::CSELWr));
+ return true;
+ case AArch64::I64CTSELECT:
+ expandCtSelect(MBB, MI, DL, get(AArch64::CSELXr));
+ return true;
+ case AArch64::BF16CTSELECT:
+ expandCtSelect(MBB, MI, DL, get(AArch64::FCSELHrrr));
+ return true;
+ case AArch64::F16CTSELECT:
+ expandCtSelect(MBB, MI, DL, get(AArch64::FCSELHrrr));
+ return true;
+ case AArch64::F32CTSELECT:
+ expandCtSelect(MBB, MI, DL, get(AArch64::FCSELSrrr));
+ return true;
+ case AArch64::F64CTSELECT:
+ expandCtSelect(MBB, MI, DL, get(AArch64::FCSELDrrr));
+ return true;
}
if (MI.getOpcode() != TargetOpcode::LOAD_STACK_GUARD &&
@@ -5118,8 +5119,7 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
.addImm(0)
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
}
- } else if (SrcReg == AArch64::WZR &&
- Subtarget.hasZeroCycleZeroingGPR64() &&
+ } else if (SrcReg == AArch64::WZR && Subtarget.hasZeroCycleZeroingGPR64()
&&
!Subtarget.hasZeroCycleZeroingGPR32()) {
// Use 64-bit zeroing when available but 32-bit zeroing is not
MCRegister DestRegX = RI.getMatchingSuperReg(DestReg, AArch64::sub_32,
``````````
</details>
https://github.com/llvm/llvm-project/pull/166706
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