https://github.com/clairechingching created https://github.com/llvm/llvm-project/pull/167013
This proposal adds a `cl::opt` CLI flag `-bpf-allow-misaligned-mem-access` to BPF target that lets users enable allowing misaligned memory accesses. The motivation behind the proposal is user space eBPF VMs (interpreters or JITs running in user space) typically run on real CPUs where unaligned memory accesses are acceptable (or handled efficiently) and can be enabled to simplify lowering and improve performance. In contrast, kernel eBPF must obey verifier constraints and platform-specific alignment restrictions. A new CLI option keeps kernel behavior unchanged while giving userspace VMs an explicit opt-in to enable more permissive codegen. It supports both use-cases without diverging codebases. >From abaf0b6497cea283f985b012bf1b625fad8f0b15 Mon Sep 17 00:00:00 2001 From: Claire xyz <[email protected]> Date: Fri, 7 Nov 2025 11:08:47 -0500 Subject: [PATCH 1/6] [BPF] Add CLI option to enable misaligned memory access --- llvm/lib/Target/BPF/BPFISelLowering.cpp | 24 ++ llvm/lib/Target/BPF/BPFISelLowering.h | 4 + llvm/test/CodeGen/BPF/unaligned_load_store.ll | 208 ++++++++++++++++++ 3 files changed, 236 insertions(+) create mode 100644 llvm/test/CodeGen/BPF/unaligned_load_store.ll diff --git a/llvm/lib/Target/BPF/BPFISelLowering.cpp b/llvm/lib/Target/BPF/BPFISelLowering.cpp index f4f414d192df0..c3ce25237637e 100644 --- a/llvm/lib/Target/BPF/BPFISelLowering.cpp +++ b/llvm/lib/Target/BPF/BPFISelLowering.cpp @@ -38,6 +38,10 @@ static cl::opt<bool> BPFExpandMemcpyInOrder("bpf-expand-memcpy-in-order", cl::Hidden, cl::init(false), cl::desc("Expand memcpy into load/store pairs in order")); +static cl::opt<bool> BPFAllowMisalignedMemAccess("bpf-allow-misaligned-mem-access", + cl::Hidden, cl::init(false), + cl::desc("Allow misaligned memory access")); + static void fail(const SDLoc &DL, SelectionDAG &DAG, const Twine &Msg, SDValue Val = {}) { std::string Str; @@ -198,6 +202,26 @@ BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM, HasMovsx = STI.hasMovsx(); } +bool BPFTargetLowering::allowsMisalignedMemoryAccesses( + EVT VT, unsigned, Align, MachineMemOperand::Flags, unsigned *Fast) const { + if (!BPFAllowMisalignedMemAccess) { + // --bpf-allow-misaligned-mem-access isn't opted in + return false; + } + + if (!VT.isSimple()) { + // only allow misalignment for simple value types + return false; + } + + if (Fast) { + // always assume fast mode when BPFAllowMisalignedMemAccess is enabled + *Fast = true; + } + + return true; +} + bool BPFTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { return false; } diff --git a/llvm/lib/Target/BPF/BPFISelLowering.h b/llvm/lib/Target/BPF/BPFISelLowering.h index 8f60261c10e9e..0b9ece5ab18c4 100644 --- a/llvm/lib/Target/BPF/BPFISelLowering.h +++ b/llvm/lib/Target/BPF/BPFISelLowering.h @@ -46,6 +46,10 @@ class BPFTargetLowering : public TargetLowering { // with the given GlobalAddress is legal. bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; + bool allowsMisalignedMemoryAccesses(EVT VT, unsigned, Align, + MachineMemOperand::Flags, + unsigned *) const override; + BPFTargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override; diff --git a/llvm/test/CodeGen/BPF/unaligned_load_store.ll b/llvm/test/CodeGen/BPF/unaligned_load_store.ll new file mode 100644 index 0000000000000..c01de4623af97 --- /dev/null +++ b/llvm/test/CodeGen/BPF/unaligned_load_store.ll @@ -0,0 +1,208 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 + +; RUN: llc -mtriple=bpfel -bpf-allow-misaligned-mem-access -verify-machineinstrs %s -o - \ +; RUN: | FileCheck --check-prefixes=ALL,MISALIGN %s +; RUN: llc -mtriple=bpfeb -bpf-allow-misaligned-mem-access -verify-machineinstrs %s -o - \ +; RUN: | FileCheck --check-prefixes=ALL,MISALIGN %s + +; RUN: llc -mtriple=bpfel -verify-machineinstrs %s -o - \ +; RUN: | FileCheck --check-prefixes=ALL,ALIGN %s +; RUN: llc -mtriple=bpfeb -verify-machineinstrs %s -o - \ +; RUN: | FileCheck --check-prefixes=ALL,ALIGN %s +; NOTE: +; This test verifies that the new +bpf-allow-misaligned-mem-access +; feature allows the BPF backend to emit direct unaligned load/store +; instructions instead of byte-by-byte emulation sequences. + +; --------------------------------------------------------------------- +; i8 load +; --------------------------------------------------------------------- +define i8 @test_load_i8(i8* %p) { +; ALL-LABEL: test_load_i8: +; ALL: # %bb.0: +; ALL-NEXT: w{{[0-9]+}} = *(u8 *)(r1 + 0) +; ALL-NEXT: exit + %v = load i8, i8* %p, align 1 + ret i8 %v +} + +; --------------------------------------------------------------------- +; i8 store +; --------------------------------------------------------------------- +define void @test_store_i8(i8* %p, i8 %v) { +; ALL-LABEL: test_store_i8: +; ALL: # %bb.0: +; ALL-NEXT: *(u8 *)(r1 + 0) = w2 +; ALL-NEXT: exit + store i8 %v, i8* %p, align 1 + ret void +} + +; --------------------------------------------------------------------- +; i16 load +; --------------------------------------------------------------------- +define i16 @test_load_i16(i16* %p) { +; MISALIGN-LABEL: test_load_i16: +; MISALIGN: # %bb.0: +; MISCHECK: w{{[0-9]+}} = *(u16 *)(r1 + 0) +; MISCHECK: exit +; +; ALIGN-LABEL: test_load_i16: +; ALIGN: # %bb.0: +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: w{{[0-9]+}} <<= 8 +; CHECK: w{{[0-9]+}} |= w{{[0-9]+}} +; CHECK: exit + %v = load i16, i16* %p, align 1 + ret i16 %v +} + +; --------------------------------------------------------------------- +; i16 store +; --------------------------------------------------------------------- +define void @test_store_i16(i16* %p, i16 %v) { +; MISALIGN-LABEL: test_store_i16: +; MISALIGN: # %bb.0: +; MISCHECK: *(u16 *)(r1 + 0) = w2 +; MISCHECK: exit +; +; ALIGN-LABEL: test_store_i16: +; ALIGN: # %bb.0: +; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: w{{[0-9]+}} >>= 8 +; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: exit + store i16 %v, i16* %p, align 1 + ret void +} + +; --------------------------------------------------------------------- +; i32 load +; --------------------------------------------------------------------- + +define i32 @test_load_i32(i32* %p) { +; MISALIGN-LABEL: test_load_i32: +; MISALIGN: # %bb.0: +; MISCHECK: w{{[0-9]+}} = *(u32 *)(r1 + 0) +; MISCHECK: exit +; +; ALIGN-LABEL: test_load_i32: +; ALIGN: # %bb.0: +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: w{{[0-9]+}} <<= 8 +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: w{{[0-9]+}} |= w{{[0-9]+}} +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: w{{[0-9]+}} <<= 16 +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: w{{[0-9]+}} <<= 24 +; CHECK: w{{[0-9]+}} |= w{{[0-9]+}} +; CHECK: w{{[0-9]+}} |= w{{[0-9]+}} +; CHECK: exit + %v = load i32, i32* %p, align 1 + ret i32 %v +} + +; --------------------------------------------------------------------- +; i32 store +; --------------------------------------------------------------------- + +define void @test_store_i32(i32* %p, i32 %v) { +; MISALIGN-LABEL: test_store_i32: +; MISALIGN: # %bb.0: +; MISCHECK: *(u32 *)(r1 + 0) = w{{[0-9]+}} +; MISCHECK: exit +; +; ALIGN-LABEL: test_store_i32: +; ALIGN: # %bb.0: +; CHECK: w{{[0-9]+}} = w{{[0-9]+}} +; CHECK: w{{[0-9]+}} >>= 24 +; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: w{{[0-9]+}} = w{{[0-9]+}} +; CHECK: w{{[0-9]+}} >>= 16 +; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: w{{[0-9]+}} >>= 8 +; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: exit + store i32 %v, i32* %p, align 1 + ret void +} + +; --------------------------------------------------------------------- +; i64 load +; --------------------------------------------------------------------- + +define i64 @test_load_i64(i64* %p) { +; MISALIGN-LABEL: test_load_i64: +; MISALIGN: # %bb.0: +; MISCHECK: r0 = *(u64 *)(r1 + 0) +; MISCHECK: exit +; +; ALIGN-LABEL: test_load_i64: +; ALIGN: # %bb.0: +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: r3 <<= 8 +; CHECK: r3 |= r2 +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: r4 <<= 16 +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: r2 <<= 24 +; CHECK: r2 |= r4 +; CHECK: r2 |= r3 +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: w{{[0-9]+}} <<= 8 +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: w{{[0-9]+}} |= w{{[0-9]+}} +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: w{{[0-9]+}} <<= 16 +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: w{{[0-9]+}} <<= 24 +; CHECK: w{{[0-9]+}} |= w{{[0-9]+}} +; CHECK: w{{[0-9]+}} |= w{{[0-9]+}} +; CHECK: r0 <<= 32 +; CHECK: r0 |= r2 +; CHECK: exit + %v = load i64, i64* %p, align 1 + ret i64 %v +} + +; --------------------------------------------------------------------- +; i64 store +; --------------------------------------------------------------------- + +define void @test_store_i64(i64* %p, i64 %v) { +; MISALIGN-LABEL: test_store_i64: +; MISALIGN: # %bb.0: +; MISCHECK: *(u64 *)(r1 + 0) = r2 +; MISCHECK: exit +; +; ALIGN-LABEL: test_store_i64: +; ALIGN: # %bb.0: +; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: r3 = r2 +; CHECK: r3 >>= 56 +; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: r3 = r2 +; CHECK: r3 >>= 48 +; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: r3 = r2 +; CHECK: r3 >>= 40 +; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: r3 = r2 +; CHECK: r3 >>= 32 +; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: r3 = r2 +; CHECK: r3 >>= 24 +; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: r3 = r2 +; CHECK: r3 >>= 16 +; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: r2 >>= 8 +; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: exit + store i64 %v, i64* %p, align 1 + ret void +} >From 5f55a3efcbc07619fb0b542d264922698c8839cb Mon Sep 17 00:00:00 2001 From: Claire xyz <[email protected]> Date: Fri, 7 Nov 2025 14:25:23 -0500 Subject: [PATCH 2/6] test: lock down with better pattern --- llvm/test/CodeGen/BPF/unaligned_load_store.ll | 56 +++++++++---------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/llvm/test/CodeGen/BPF/unaligned_load_store.ll b/llvm/test/CodeGen/BPF/unaligned_load_store.ll index c01de4623af97..0ea4ced544218 100644 --- a/llvm/test/CodeGen/BPF/unaligned_load_store.ll +++ b/llvm/test/CodeGen/BPF/unaligned_load_store.ll @@ -49,8 +49,8 @@ define i16 @test_load_i16(i16* %p) { ; ; ALIGN-LABEL: test_load_i16: ; ALIGN: # %bb.0: -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 0) +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 1) ; CHECK: w{{[0-9]+}} <<= 8 ; CHECK: w{{[0-9]+}} |= w{{[0-9]+}} ; CHECK: exit @@ -69,9 +69,9 @@ define void @test_store_i16(i16* %p, i16 %v) { ; ; ALIGN-LABEL: test_store_i16: ; ALIGN: # %bb.0: -; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: *(u8 *)(r1 + 0) = w{{[0-9]+}} ; CHECK: w{{[0-9]+}} >>= 8 -; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: *(u8 *)(r1 + 1) = w{{[0-9]+}} ; CHECK: exit store i16 %v, i16* %p, align 1 ret void @@ -89,13 +89,13 @@ define i32 @test_load_i32(i32* %p) { ; ; ALIGN-LABEL: test_load_i32: ; ALIGN: # %bb.0: -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 0) ; CHECK: w{{[0-9]+}} <<= 8 -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 1) ; CHECK: w{{[0-9]+}} |= w{{[0-9]+}} -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 2) ; CHECK: w{{[0-9]+}} <<= 16 -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 3) ; CHECK: w{{[0-9]+}} <<= 24 ; CHECK: w{{[0-9]+}} |= w{{[0-9]+}} ; CHECK: w{{[0-9]+}} |= w{{[0-9]+}} @@ -118,13 +118,13 @@ define void @test_store_i32(i32* %p, i32 %v) { ; ALIGN: # %bb.0: ; CHECK: w{{[0-9]+}} = w{{[0-9]+}} ; CHECK: w{{[0-9]+}} >>= 24 -; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: *(u8 *)(r1 + 0) = w{{[0-9]+}} ; CHECK: w{{[0-9]+}} = w{{[0-9]+}} ; CHECK: w{{[0-9]+}} >>= 16 -; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} -; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: *(u8 *)(r1 + 1) = w{{[0-9]+}} +; CHECK: *(u8 *)(r1 + 2) = w{{[0-9]+}} ; CHECK: w{{[0-9]+}} >>= 8 -; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: *(u8 *)(r1 + 3) = w{{[0-9]+}} ; CHECK: exit store i32 %v, i32* %p, align 1 ret void @@ -142,23 +142,23 @@ define i64 @test_load_i64(i64* %p) { ; ; ALIGN-LABEL: test_load_i64: ; ALIGN: # %bb.0: -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 0) +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 1) ; CHECK: r3 <<= 8 ; CHECK: r3 |= r2 -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 2) ; CHECK: r4 <<= 16 -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 3) ; CHECK: r2 <<= 24 ; CHECK: r2 |= r4 ; CHECK: r2 |= r3 -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 4) ; CHECK: w{{[0-9]+}} <<= 8 -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 5) ; CHECK: w{{[0-9]+}} |= w{{[0-9]+}} -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 6) ; CHECK: w{{[0-9]+}} <<= 16 -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + [[OFFSET:[0-9]+]]) +; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 7) ; CHECK: w{{[0-9]+}} <<= 24 ; CHECK: w{{[0-9]+}} |= w{{[0-9]+}} ; CHECK: w{{[0-9]+}} |= w{{[0-9]+}} @@ -181,27 +181,27 @@ define void @test_store_i64(i64* %p, i64 %v) { ; ; ALIGN-LABEL: test_store_i64: ; ALIGN: # %bb.0: -; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: *(u8 *)(r1 + 0) = w{{[0-9]+}} ; CHECK: r3 = r2 ; CHECK: r3 >>= 56 -; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: *(u8 *)(r1 + 1) = w{{[0-9]+}} ; CHECK: r3 = r2 ; CHECK: r3 >>= 48 -; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: *(u8 *)(r1 + 2) = w{{[0-9]+}} ; CHECK: r3 = r2 ; CHECK: r3 >>= 40 -; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: *(u8 *)(r1 + 3) = w{{[0-9]+}} ; CHECK: r3 = r2 ; CHECK: r3 >>= 32 -; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: *(u8 *)(r1 + 4) = w{{[0-9]+}} ; CHECK: r3 = r2 ; CHECK: r3 >>= 24 -; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: *(u8 *)(r1 + 5) = w{{[0-9]+}} ; CHECK: r3 = r2 ; CHECK: r3 >>= 16 -; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: *(u8 *)(r1 + 6) = w{{[0-9]+}} ; CHECK: r2 >>= 8 -; CHECK: *(u8 *)(r1 + [[OFFSET:[0-9]+]]) = w{{[0-9]+}} +; CHECK: *(u8 *)(r1 + 7) = w{{[0-9]+}} ; CHECK: exit store i64 %v, i64* %p, align 1 ret void >From 517e26c64158572cde9b37469a909f1e2bcf93ab Mon Sep 17 00:00:00 2001 From: Claire xyz <[email protected]> Date: Fri, 7 Nov 2025 14:44:04 -0500 Subject: [PATCH 3/6] fix test: wasn't really enabled by CHECK label --- llvm/test/CodeGen/BPF/unaligned_load_store.ll | 174 +++++++++--------- 1 file changed, 87 insertions(+), 87 deletions(-) diff --git a/llvm/test/CodeGen/BPF/unaligned_load_store.ll b/llvm/test/CodeGen/BPF/unaligned_load_store.ll index 0ea4ced544218..f2ddb174519f0 100644 --- a/llvm/test/CodeGen/BPF/unaligned_load_store.ll +++ b/llvm/test/CodeGen/BPF/unaligned_load_store.ll @@ -44,16 +44,16 @@ define void @test_store_i8(i8* %p, i8 %v) { define i16 @test_load_i16(i16* %p) { ; MISALIGN-LABEL: test_load_i16: ; MISALIGN: # %bb.0: -; MISCHECK: w{{[0-9]+}} = *(u16 *)(r1 + 0) -; MISCHECK: exit +; MISALIGN: w{{[0-9]+}} = *(u16 *)(r1 + 0) +; MISALIGN: exit ; ; ALIGN-LABEL: test_load_i16: ; ALIGN: # %bb.0: -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 0) -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 1) -; CHECK: w{{[0-9]+}} <<= 8 -; CHECK: w{{[0-9]+}} |= w{{[0-9]+}} -; CHECK: exit +; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 0) +; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 1) +; ALIGN-DAG: w{{[0-9]+}} <<= 8 +; ALIGN-DAG: w{{[0-9]+}} |= w{{[0-9]+}} +; ALIGN: exit %v = load i16, i16* %p, align 1 ret i16 %v } @@ -64,15 +64,15 @@ define i16 @test_load_i16(i16* %p) { define void @test_store_i16(i16* %p, i16 %v) { ; MISALIGN-LABEL: test_store_i16: ; MISALIGN: # %bb.0: -; MISCHECK: *(u16 *)(r1 + 0) = w2 -; MISCHECK: exit +; MISALIGN: *(u16 *)(r1 + 0) = w2 +; MISALIGN: exit ; ; ALIGN-LABEL: test_store_i16: ; ALIGN: # %bb.0: -; CHECK: *(u8 *)(r1 + 0) = w{{[0-9]+}} -; CHECK: w{{[0-9]+}} >>= 8 -; CHECK: *(u8 *)(r1 + 1) = w{{[0-9]+}} -; CHECK: exit +; ALIGN-DAG: *(u8 *)(r1 + 0) = w{{[0-9]+}} +; ALIGN-DAG: w{{[0-9]+}} >>= 8 +; ALIGN-DAG: *(u8 *)(r1 + 1) = w{{[0-9]+}} +; ALIGN: exit store i16 %v, i16* %p, align 1 ret void } @@ -84,22 +84,22 @@ define void @test_store_i16(i16* %p, i16 %v) { define i32 @test_load_i32(i32* %p) { ; MISALIGN-LABEL: test_load_i32: ; MISALIGN: # %bb.0: -; MISCHECK: w{{[0-9]+}} = *(u32 *)(r1 + 0) -; MISCHECK: exit +; MISALIGN: w{{[0-9]+}} = *(u32 *)(r1 + 0) +; MISALIGN: exit ; ; ALIGN-LABEL: test_load_i32: ; ALIGN: # %bb.0: -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 0) -; CHECK: w{{[0-9]+}} <<= 8 -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 1) -; CHECK: w{{[0-9]+}} |= w{{[0-9]+}} -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 2) -; CHECK: w{{[0-9]+}} <<= 16 -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 3) -; CHECK: w{{[0-9]+}} <<= 24 -; CHECK: w{{[0-9]+}} |= w{{[0-9]+}} -; CHECK: w{{[0-9]+}} |= w{{[0-9]+}} -; CHECK: exit +; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 0) +; ALIGN-DAG: w{{[0-9]+}} <<= 8 +; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 1) +; ALIGN-DAG: w{{[0-9]+}} |= w{{[0-9]+}} +; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 2) +; ALIGN-DAG: w{{[0-9]+}} <<= 16 +; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 3) +; ALIGN-DAG: w{{[0-9]+}} <<= 24 +; ALIGN-DAG: w{{[0-9]+}} |= w{{[0-9]+}} +; ALIGN-DAG: w{{[0-9]+}} |= w{{[0-9]+}} +; ALIGN: exit %v = load i32, i32* %p, align 1 ret i32 %v } @@ -111,21 +111,21 @@ define i32 @test_load_i32(i32* %p) { define void @test_store_i32(i32* %p, i32 %v) { ; MISALIGN-LABEL: test_store_i32: ; MISALIGN: # %bb.0: -; MISCHECK: *(u32 *)(r1 + 0) = w{{[0-9]+}} -; MISCHECK: exit +; MISALIGN: *(u32 *)(r1 + 0) = w{{[0-9]+}} +; MISALIGN: exit ; ; ALIGN-LABEL: test_store_i32: ; ALIGN: # %bb.0: -; CHECK: w{{[0-9]+}} = w{{[0-9]+}} -; CHECK: w{{[0-9]+}} >>= 24 -; CHECK: *(u8 *)(r1 + 0) = w{{[0-9]+}} -; CHECK: w{{[0-9]+}} = w{{[0-9]+}} -; CHECK: w{{[0-9]+}} >>= 16 -; CHECK: *(u8 *)(r1 + 1) = w{{[0-9]+}} -; CHECK: *(u8 *)(r1 + 2) = w{{[0-9]+}} -; CHECK: w{{[0-9]+}} >>= 8 -; CHECK: *(u8 *)(r1 + 3) = w{{[0-9]+}} -; CHECK: exit +; ALIGN-DAG: w{{[0-9]+}} = w{{[0-9]+}} +; ALIGN-DAG: w{{[0-9]+}} >>= 24 +; ALIGN-DAG: *(u8 *)(r1 + 0) = w{{[0-9]+}} +; ALIGN-DAG: w{{[0-9]+}} = w{{[0-9]+}} +; ALIGN-DAG: w{{[0-9]+}} >>= 16 +; ALIGN-DAG: *(u8 *)(r1 + 1) = w{{[0-9]+}} +; ALIGN-DAG: *(u8 *)(r1 + 2) = w{{[0-9]+}} +; ALIGN-DAG: w{{[0-9]+}} >>= 8 +; ALIGN-DAG: *(u8 *)(r1 + 3) = w{{[0-9]+}} +; ALIGN: exit store i32 %v, i32* %p, align 1 ret void } @@ -137,34 +137,34 @@ define void @test_store_i32(i32* %p, i32 %v) { define i64 @test_load_i64(i64* %p) { ; MISALIGN-LABEL: test_load_i64: ; MISALIGN: # %bb.0: -; MISCHECK: r0 = *(u64 *)(r1 + 0) -; MISCHECK: exit +; MISALIGN: r0 = *(u64 *)(r1 + 0) +; MISALIGN: exit ; ; ALIGN-LABEL: test_load_i64: ; ALIGN: # %bb.0: -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 0) -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 1) -; CHECK: r3 <<= 8 -; CHECK: r3 |= r2 -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 2) -; CHECK: r4 <<= 16 -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 3) -; CHECK: r2 <<= 24 -; CHECK: r2 |= r4 -; CHECK: r2 |= r3 -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 4) -; CHECK: w{{[0-9]+}} <<= 8 -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 5) -; CHECK: w{{[0-9]+}} |= w{{[0-9]+}} -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 6) -; CHECK: w{{[0-9]+}} <<= 16 -; CHECK: w{{[0-9]+}} = *(u8 *)(r1 + 7) -; CHECK: w{{[0-9]+}} <<= 24 -; CHECK: w{{[0-9]+}} |= w{{[0-9]+}} -; CHECK: w{{[0-9]+}} |= w{{[0-9]+}} -; CHECK: r0 <<= 32 -; CHECK: r0 |= r2 -; CHECK: exit +; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 0) +; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 1) +; ALIGN-DAG: r3 <<= 8 +; ALIGN-DAG: r3 |= r2 +; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 2) +; ALIGN-DAG: r4 <<= 16 +; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 3) +; ALIGN-DAG: r2 <<= 24 +; ALIGN-DAG: r2 |= r4 +; ALIGN-DAG: r2 |= r3 +; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 4) +; ALIGN-DAG: w{{[0-9]+}} <<= 8 +; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 5) +; ALIGN-DAG: w{{[0-9]+}} |= w{{[0-9]+}} +; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 6) +; ALIGN-DAG: w{{[0-9]+}} <<= 16 +; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 7) +; ALIGN-DAG: w{{[0-9]+}} <<= 24 +; ALIGN-DAG: w{{[0-9]+}} |= w{{[0-9]+}} +; ALIGN-DAG: w{{[0-9]+}} |= w{{[0-9]+}} +; ALIGN-DAG: r0 <<= 32 +; ALIGN-DAG: r0 |= r2 +; ALIGN: exit %v = load i64, i64* %p, align 1 ret i64 %v } @@ -176,33 +176,33 @@ define i64 @test_load_i64(i64* %p) { define void @test_store_i64(i64* %p, i64 %v) { ; MISALIGN-LABEL: test_store_i64: ; MISALIGN: # %bb.0: -; MISCHECK: *(u64 *)(r1 + 0) = r2 -; MISCHECK: exit +; MISALIGN: *(u64 *)(r1 + 0) = r2 +; MISALIGN: exit ; ; ALIGN-LABEL: test_store_i64: ; ALIGN: # %bb.0: -; CHECK: *(u8 *)(r1 + 0) = w{{[0-9]+}} -; CHECK: r3 = r2 -; CHECK: r3 >>= 56 -; CHECK: *(u8 *)(r1 + 1) = w{{[0-9]+}} -; CHECK: r3 = r2 -; CHECK: r3 >>= 48 -; CHECK: *(u8 *)(r1 + 2) = w{{[0-9]+}} -; CHECK: r3 = r2 -; CHECK: r3 >>= 40 -; CHECK: *(u8 *)(r1 + 3) = w{{[0-9]+}} -; CHECK: r3 = r2 -; CHECK: r3 >>= 32 -; CHECK: *(u8 *)(r1 + 4) = w{{[0-9]+}} -; CHECK: r3 = r2 -; CHECK: r3 >>= 24 -; CHECK: *(u8 *)(r1 + 5) = w{{[0-9]+}} -; CHECK: r3 = r2 -; CHECK: r3 >>= 16 -; CHECK: *(u8 *)(r1 + 6) = w{{[0-9]+}} -; CHECK: r2 >>= 8 -; CHECK: *(u8 *)(r1 + 7) = w{{[0-9]+}} -; CHECK: exit +; ALIGN-DAG: *(u8 *)(r1 + 0) = w{{[0-9]+}} +; ALIGN-DAG: r3 = r2 +; ALIGN-DAG: r{{[0-9]+}} >>= 56 +; ALIGN-DAG: *(u8 *)(r1 + 1) = w{{[0-9]+}} +; ALIGN-DAG: r3 = r2 +; ALIGN-DAG: r{{[0-9]+}} >>= 48 +; ALIGN-DAG: *(u8 *)(r1 + 2) = w{{[0-9]+}} +; ALIGN-DAG: r3 = r2 +; ALIGN-DAG: r{{[0-9]+}} >>= 40 +; ALIGN-DAG: *(u8 *)(r1 + 3) = w{{[0-9]+}} +; ALIGN-DAG: r3 = r2 +; ALIGN-DAG: r{{[0-9]+}} >>= 32 +; ALIGN-DAG: *(u8 *)(r1 + 4) = w{{[0-9]+}} +; ALIGN-DAG: r3 = r2 +; ALIGN-DAG: r{{[0-9]+}} >>= 24 +; ALIGN-DAG: *(u8 *)(r1 + 5) = w{{[0-9]+}} +; ALIGN-DAG: r3 = r2 +; ALIGN-DAG: r{{[0-9]+}} >>= 16 +; ALIGN-DAG: *(u8 *)(r1 + 6) = w{{[0-9]+}} +; ALIGN-DAG: r{{[0-9]+}} >>= 8 +; ALIGN-DAG: *(u8 *)(r1 + 7) = w{{[0-9]+}} +; ALIGN: exit store i64 %v, i64* %p, align 1 ret void } >From 53dacb749d3d97f47ab91a9fc11a28b31c26e849 Mon Sep 17 00:00:00 2001 From: Claire xyz <[email protected]> Date: Fri, 7 Nov 2025 14:49:29 -0500 Subject: [PATCH 4/6] test: lock down with bettern pattern --- llvm/test/CodeGen/BPF/unaligned_load_store.ll | 20 ++++++------------- 1 file changed, 6 insertions(+), 14 deletions(-) diff --git a/llvm/test/CodeGen/BPF/unaligned_load_store.ll b/llvm/test/CodeGen/BPF/unaligned_load_store.ll index f2ddb174519f0..07599e9a33303 100644 --- a/llvm/test/CodeGen/BPF/unaligned_load_store.ll +++ b/llvm/test/CodeGen/BPF/unaligned_load_store.ll @@ -144,14 +144,12 @@ define i64 @test_load_i64(i64* %p) { ; ALIGN: # %bb.0: ; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 0) ; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 1) -; ALIGN-DAG: r3 <<= 8 -; ALIGN-DAG: r3 |= r2 +; ALIGN-DAG: r{{[0-9]+}} <<= 8 +; ALIGN-DAG: r{{[0-9]+}} |= r{{[0-9]+}} ; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 2) -; ALIGN-DAG: r4 <<= 16 +; ALIGN-DAG: r{{[0-9]+}} <<= 16 ; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 3) -; ALIGN-DAG: r2 <<= 24 -; ALIGN-DAG: r2 |= r4 -; ALIGN-DAG: r2 |= r3 +; ALIGN-DAG: r{{[0-9]+}} <<= 24 ; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 4) ; ALIGN-DAG: w{{[0-9]+}} <<= 8 ; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 5) @@ -162,8 +160,7 @@ define i64 @test_load_i64(i64* %p) { ; ALIGN-DAG: w{{[0-9]+}} <<= 24 ; ALIGN-DAG: w{{[0-9]+}} |= w{{[0-9]+}} ; ALIGN-DAG: w{{[0-9]+}} |= w{{[0-9]+}} -; ALIGN-DAG: r0 <<= 32 -; ALIGN-DAG: r0 |= r2 +; ALIGN-DAG: r{{[0-9]+}} <<= 32 ; ALIGN: exit %v = load i64, i64* %p, align 1 ret i64 %v @@ -182,22 +179,17 @@ define void @test_store_i64(i64* %p, i64 %v) { ; ALIGN-LABEL: test_store_i64: ; ALIGN: # %bb.0: ; ALIGN-DAG: *(u8 *)(r1 + 0) = w{{[0-9]+}} -; ALIGN-DAG: r3 = r2 +; ALIGN-DAG: r{{[0-9]+}} = r{{[0-9]+}} ; ALIGN-DAG: r{{[0-9]+}} >>= 56 ; ALIGN-DAG: *(u8 *)(r1 + 1) = w{{[0-9]+}} -; ALIGN-DAG: r3 = r2 ; ALIGN-DAG: r{{[0-9]+}} >>= 48 ; ALIGN-DAG: *(u8 *)(r1 + 2) = w{{[0-9]+}} -; ALIGN-DAG: r3 = r2 ; ALIGN-DAG: r{{[0-9]+}} >>= 40 ; ALIGN-DAG: *(u8 *)(r1 + 3) = w{{[0-9]+}} -; ALIGN-DAG: r3 = r2 ; ALIGN-DAG: r{{[0-9]+}} >>= 32 ; ALIGN-DAG: *(u8 *)(r1 + 4) = w{{[0-9]+}} -; ALIGN-DAG: r3 = r2 ; ALIGN-DAG: r{{[0-9]+}} >>= 24 ; ALIGN-DAG: *(u8 *)(r1 + 5) = w{{[0-9]+}} -; ALIGN-DAG: r3 = r2 ; ALIGN-DAG: r{{[0-9]+}} >>= 16 ; ALIGN-DAG: *(u8 *)(r1 + 6) = w{{[0-9]+}} ; ALIGN-DAG: r{{[0-9]+}} >>= 8 >From 06651dd3171fa65b4087e7159d77777fb6473ea6 Mon Sep 17 00:00:00 2001 From: Claire xyz <[email protected]> Date: Fri, 7 Nov 2025 14:53:40 -0500 Subject: [PATCH 5/6] test: lock down with bettern pattern --- llvm/test/CodeGen/BPF/unaligned_load_store.ll | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/llvm/test/CodeGen/BPF/unaligned_load_store.ll b/llvm/test/CodeGen/BPF/unaligned_load_store.ll index 07599e9a33303..cdf2cd36769c8 100644 --- a/llvm/test/CodeGen/BPF/unaligned_load_store.ll +++ b/llvm/test/CodeGen/BPF/unaligned_load_store.ll @@ -32,7 +32,7 @@ define i8 @test_load_i8(i8* %p) { define void @test_store_i8(i8* %p, i8 %v) { ; ALL-LABEL: test_store_i8: ; ALL: # %bb.0: -; ALL-NEXT: *(u8 *)(r1 + 0) = w2 +; ALL-NEXT: *(u8 *)(r1 + 0) = w{{[0-9]+}} ; ALL-NEXT: exit store i8 %v, i8* %p, align 1 ret void @@ -64,7 +64,7 @@ define i16 @test_load_i16(i16* %p) { define void @test_store_i16(i16* %p, i16 %v) { ; MISALIGN-LABEL: test_store_i16: ; MISALIGN: # %bb.0: -; MISALIGN: *(u16 *)(r1 + 0) = w2 +; MISALIGN: *(u16 *)(r1 + 0) = w{{[0-9]+}} ; MISALIGN: exit ; ; ALIGN-LABEL: test_store_i16: @@ -97,8 +97,6 @@ define i32 @test_load_i32(i32* %p) { ; ALIGN-DAG: w{{[0-9]+}} <<= 16 ; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 3) ; ALIGN-DAG: w{{[0-9]+}} <<= 24 -; ALIGN-DAG: w{{[0-9]+}} |= w{{[0-9]+}} -; ALIGN-DAG: w{{[0-9]+}} |= w{{[0-9]+}} ; ALIGN: exit %v = load i32, i32* %p, align 1 ret i32 %v >From d58f2eb39493ef7dd2ef24a630bbcf15e0efa53d Mon Sep 17 00:00:00 2001 From: Claire xyz <[email protected]> Date: Fri, 7 Nov 2025 14:59:29 -0500 Subject: [PATCH 6/6] test: lock down with bettern pattern --- llvm/test/CodeGen/BPF/unaligned_load_store.ll | 2 -- 1 file changed, 2 deletions(-) diff --git a/llvm/test/CodeGen/BPF/unaligned_load_store.ll b/llvm/test/CodeGen/BPF/unaligned_load_store.ll index cdf2cd36769c8..9ddbd7e64f7bf 100644 --- a/llvm/test/CodeGen/BPF/unaligned_load_store.ll +++ b/llvm/test/CodeGen/BPF/unaligned_load_store.ll @@ -156,8 +156,6 @@ define i64 @test_load_i64(i64* %p) { ; ALIGN-DAG: w{{[0-9]+}} <<= 16 ; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 7) ; ALIGN-DAG: w{{[0-9]+}} <<= 24 -; ALIGN-DAG: w{{[0-9]+}} |= w{{[0-9]+}} -; ALIGN-DAG: w{{[0-9]+}} |= w{{[0-9]+}} ; ALIGN-DAG: r{{[0-9]+}} <<= 32 ; ALIGN: exit %v = load i64, i64* %p, align 1 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
