https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/165962
>From 68599da762a0ae344052c7e489545c227009d12c Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Fri, 31 Oct 2025 18:24:27 -0700 Subject: [PATCH] CodeGen: Remove target hook for terminal rule Enables the terminal rule for remaining targets --- llvm/lib/CodeGen/RegisterCoalescer.cpp | 12 +- llvm/lib/Target/AArch64/AArch64Subtarget.h | 2 +- llvm/lib/Target/AMDGPU/GCNSubtarget.h | 2 - llvm/lib/Target/AMDGPU/R600Subtarget.h | 2 - llvm/lib/Target/ARM/ARMSubtarget.h | 1 - llvm/lib/Target/Hexagon/HexagonSubtarget.h | 2 - llvm/lib/Target/RISCV/RISCVSubtarget.h | 1 - llvm/lib/Target/X86/X86Subtarget.h | 2 - llvm/test/CodeGen/BPF/objdump_cond_op_2.ll | 3 +- llvm/test/CodeGen/NVPTX/atomics-b128.ll | 150 +++++++++--------- llvm/test/CodeGen/NVPTX/atomics-sm70.ll | 40 ++--- llvm/test/CodeGen/NVPTX/atomics-sm90.ll | 40 ++--- llvm/test/CodeGen/NVPTX/atomics.ll | 12 +- llvm/test/CodeGen/PowerPC/ctrloop-fp128.ll | 6 +- llvm/test/CodeGen/PowerPC/licm-xxsplti.ll | 54 +++---- .../PowerPC/loop-instr-form-prepare.ll | 8 +- llvm/test/CodeGen/PowerPC/perfect-shuffle.ll | 12 +- llvm/test/CodeGen/PowerPC/sms-phi-1.ll | 5 +- llvm/test/CodeGen/PowerPC/sms-phi-2.ll | 43 +++-- .../test/CodeGen/SystemZ/atomicrmw-fadd-01.ll | 11 +- .../test/CodeGen/SystemZ/atomicrmw-fsub-01.ll | 11 +- .../CodeGen/WebAssembly/simd-shift-in-loop.ll | 14 +- 22 files changed, 207 insertions(+), 226 deletions(-) diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp index f93a7f22c3961..88357ad2debae 100644 --- a/llvm/lib/CodeGen/RegisterCoalescer.cpp +++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp @@ -79,9 +79,9 @@ static cl::opt<bool> EnableJoining("join-liveintervals", cl::desc("Coalesce copies (default=true)"), cl::init(true), cl::Hidden); -static cl::opt<cl::boolOrDefault> - EnableTerminalRule("terminal-rule", cl::desc("Apply the terminal rule"), - cl::init(cl::BOU_UNSET), cl::Hidden); +static cl::opt<bool> UseTerminalRule("terminal-rule", + cl::desc("Apply the terminal rule"), + cl::init(true), cl::Hidden); /// Temporary flag to test critical edge unsplitting. static cl::opt<bool> EnableJoinSplits( @@ -134,7 +134,6 @@ class RegisterCoalescer : private LiveRangeEdit::Delegate { SlotIndexes *SI = nullptr; const MachineLoopInfo *Loops = nullptr; RegisterClassInfo RegClassInfo; - bool UseTerminalRule = false; /// Position and VReg of a PHI instruction during coalescing. struct PHIValPos { @@ -4321,11 +4320,6 @@ bool RegisterCoalescer::run(MachineFunction &fn) { else JoinGlobalCopies = (EnableGlobalCopies == cl::BOU_TRUE); - if (EnableTerminalRule == cl::BOU_UNSET) - UseTerminalRule = STI.enableTerminalRule(); - else - UseTerminalRule = EnableTerminalRule == cl::BOU_TRUE; - // If there are PHIs tracked by debug-info, they will need updating during // coalescing. Build an index of those PHIs to ease updating. SlotIndexes *Slots = LIS->getSlotIndexes(); diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h index ab4004e30f629..8974965c41fe3 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -157,7 +157,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo { bool enableMachineScheduler() const override { return true; } bool enablePostRAScheduler() const override { return usePostRAScheduler(); } bool enableSubRegLiveness() const override { return EnableSubregLiveness; } - bool enableTerminalRule() const override { return true; } + bool enableMachinePipeliner() const override; bool useDFAforSMS() const override { return false; } diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h index da4bd878b8853..f377b8aaf1333 100644 --- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h +++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h @@ -1040,8 +1040,6 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo, return true; } - bool enableTerminalRule() const override { return true; } - bool useAA() const override; bool enableSubRegLiveness() const override { diff --git a/llvm/lib/Target/AMDGPU/R600Subtarget.h b/llvm/lib/Target/AMDGPU/R600Subtarget.h index efd99dbc1a08b..22e56b66e1827 100644 --- a/llvm/lib/Target/AMDGPU/R600Subtarget.h +++ b/llvm/lib/Target/AMDGPU/R600Subtarget.h @@ -126,8 +126,6 @@ class R600Subtarget final : public R600GenSubtargetInfo, return true; } - bool enableTerminalRule() const override { return true; } - bool enableSubRegLiveness() const override { return true; } diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h index 34baa3108402c..4a0883cc662e7 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.h +++ b/llvm/lib/Target/ARM/ARMSubtarget.h @@ -377,7 +377,6 @@ class ARMSubtarget : public ARMGenSubtargetInfo { bool isRWPI() const; bool useMachineScheduler() const { return UseMISched; } - bool enableTerminalRule() const override { return true; } bool useMachinePipeliner() const { return UseMIPipeliner; } bool hasMinSize() const { return OptMinSize; } bool isThumb1Only() const { return isThumb() && !hasThumb2(); } diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.h b/llvm/lib/Target/Hexagon/HexagonSubtarget.h index b3d5d010d378d..995f66d0551b4 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.h +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.h @@ -295,8 +295,6 @@ class HexagonSubtarget : public HexagonGenSubtargetInfo { bool useBSBScheduling() const { return UseBSBScheduling; } bool enableMachineScheduler() const override; - bool enableTerminalRule() const override { return true; } - // Always use the TargetLowering default scheduler. // FIXME: This will use the vliw scheduler which is probably just hurting // compiler time and will be removed eventually anyway. diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h index 817fb7cb5c41a..4b4fc8f0d8e76 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -147,7 +147,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { } bool enableMachineScheduler() const override { return true; } - bool enableTerminalRule() const override { return true; } bool enablePostRAScheduler() const override { return UsePostRAScheduler; } diff --git a/llvm/lib/Target/X86/X86Subtarget.h b/llvm/lib/Target/X86/X86Subtarget.h index 4f5aadca361fe..868f41375b96b 100644 --- a/llvm/lib/Target/X86/X86Subtarget.h +++ b/llvm/lib/Target/X86/X86Subtarget.h @@ -419,8 +419,6 @@ class X86Subtarget final : public X86GenSubtargetInfo { /// Enable the MachineScheduler pass for all X86 subtargets. bool enableMachineScheduler() const override { return true; } - bool enableTerminalRule() const override { return true; } - bool enableEarlyIfConversion() const override; void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>> diff --git a/llvm/test/CodeGen/BPF/objdump_cond_op_2.ll b/llvm/test/CodeGen/BPF/objdump_cond_op_2.ll index 895b68b5a9145..ce40085feb0d0 100644 --- a/llvm/test/CodeGen/BPF/objdump_cond_op_2.ll +++ b/llvm/test/CodeGen/BPF/objdump_cond_op_2.ll @@ -25,8 +25,7 @@ define i32 @test(i32, i32) local_unnamed_addr #0 { %11 = sub nsw i32 %7, %9 %12 = icmp slt i32 %10, %11 br i1 %12, label %5, label %13 -; CHECK: r1 = r3 -; CHECK: if r2 s> r3 goto -10 <test+0x40> +; CHECK: if r2 s> r1 goto -10 <test+0x40> ; <label>:13: ; preds = %5, %2 %14 = phi i32 [ 0, %2 ], [ %9, %5 ] diff --git a/llvm/test/CodeGen/NVPTX/atomics-b128.ll b/llvm/test/CodeGen/NVPTX/atomics-b128.ll index b2a3f94d11a16..3057e91e8ebe4 100644 --- a/llvm/test/CodeGen/NVPTX/atomics-b128.ll +++ b/llvm/test/CodeGen/NVPTX/atomics-b128.ll @@ -756,24 +756,24 @@ define i128 @test_atomicrmw_and(ptr %ptr, i128 %val) { ; CHECK-NEXT: ld.v2.b64 {%rd11, %rd12}, [%rd3]; ; CHECK-NEXT: $L__BB34_1: // %atomicrmw.start ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: and.b64 %rd6, %rd11, %rd4; -; CHECK-NEXT: and.b64 %rd7, %rd12, %rd5; +; CHECK-NEXT: mov.b64 %rd2, %rd12; +; CHECK-NEXT: mov.b64 %rd1, %rd11; +; CHECK-NEXT: and.b64 %rd6, %rd1, %rd4; +; CHECK-NEXT: and.b64 %rd7, %rd2, %rd5; ; CHECK-NEXT: { ; CHECK-NEXT: .reg .b128 cmp, swap, dst; -; CHECK-NEXT: mov.b128 cmp, {%rd11, %rd12}; +; CHECK-NEXT: mov.b128 cmp, {%rd1, %rd2}; ; CHECK-NEXT: mov.b128 swap, {%rd6, %rd7}; ; CHECK-NEXT: atom.relaxed.sys.cas.b128 dst, [%rd3], cmp, swap; -; CHECK-NEXT: mov.b128 {%rd1, %rd2}, dst; +; CHECK-NEXT: mov.b128 {%rd11, %rd12}, dst; ; CHECK-NEXT: } -; CHECK-NEXT: xor.b64 %rd8, %rd2, %rd12; -; CHECK-NEXT: xor.b64 %rd9, %rd1, %rd11; +; CHECK-NEXT: xor.b64 %rd8, %rd12, %rd2; +; CHECK-NEXT: xor.b64 %rd9, %rd11, %rd1; ; CHECK-NEXT: or.b64 %rd10, %rd9, %rd8; ; CHECK-NEXT: setp.ne.b64 %p1, %rd10, 0; -; CHECK-NEXT: mov.b64 %rd11, %rd1; -; CHECK-NEXT: mov.b64 %rd12, %rd2; ; CHECK-NEXT: @%p1 bra $L__BB34_1; ; CHECK-NEXT: // %bb.2: // %atomicrmw.end -; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd1, %rd2}; +; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd11, %rd12}; ; CHECK-NEXT: ret; %ret = atomicrmw and ptr %ptr, i128 %val monotonic ret i128 %ret @@ -791,24 +791,24 @@ define i128 @test_atomicrmw_or(ptr %ptr, i128 %val) { ; CHECK-NEXT: ld.v2.b64 {%rd11, %rd12}, [%rd3]; ; CHECK-NEXT: $L__BB35_1: // %atomicrmw.start ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: or.b64 %rd6, %rd11, %rd4; -; CHECK-NEXT: or.b64 %rd7, %rd12, %rd5; +; CHECK-NEXT: mov.b64 %rd2, %rd12; +; CHECK-NEXT: mov.b64 %rd1, %rd11; +; CHECK-NEXT: or.b64 %rd6, %rd1, %rd4; +; CHECK-NEXT: or.b64 %rd7, %rd2, %rd5; ; CHECK-NEXT: { ; CHECK-NEXT: .reg .b128 cmp, swap, dst; -; CHECK-NEXT: mov.b128 cmp, {%rd11, %rd12}; +; CHECK-NEXT: mov.b128 cmp, {%rd1, %rd2}; ; CHECK-NEXT: mov.b128 swap, {%rd6, %rd7}; ; CHECK-NEXT: atom.relaxed.sys.cas.b128 dst, [%rd3], cmp, swap; -; CHECK-NEXT: mov.b128 {%rd1, %rd2}, dst; +; CHECK-NEXT: mov.b128 {%rd11, %rd12}, dst; ; CHECK-NEXT: } -; CHECK-NEXT: xor.b64 %rd8, %rd2, %rd12; -; CHECK-NEXT: xor.b64 %rd9, %rd1, %rd11; +; CHECK-NEXT: xor.b64 %rd8, %rd12, %rd2; +; CHECK-NEXT: xor.b64 %rd9, %rd11, %rd1; ; CHECK-NEXT: or.b64 %rd10, %rd9, %rd8; ; CHECK-NEXT: setp.ne.b64 %p1, %rd10, 0; -; CHECK-NEXT: mov.b64 %rd11, %rd1; -; CHECK-NEXT: mov.b64 %rd12, %rd2; ; CHECK-NEXT: @%p1 bra $L__BB35_1; ; CHECK-NEXT: // %bb.2: // %atomicrmw.end -; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd1, %rd2}; +; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd11, %rd12}; ; CHECK-NEXT: ret; %ret = atomicrmw or ptr %ptr, i128 %val monotonic ret i128 %ret @@ -826,24 +826,24 @@ define i128 @test_atomicrmw_xor(ptr %ptr, i128 %val) { ; CHECK-NEXT: ld.v2.b64 {%rd11, %rd12}, [%rd3]; ; CHECK-NEXT: $L__BB36_1: // %atomicrmw.start ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: xor.b64 %rd6, %rd11, %rd4; -; CHECK-NEXT: xor.b64 %rd7, %rd12, %rd5; +; CHECK-NEXT: mov.b64 %rd2, %rd12; +; CHECK-NEXT: mov.b64 %rd1, %rd11; +; CHECK-NEXT: xor.b64 %rd6, %rd1, %rd4; +; CHECK-NEXT: xor.b64 %rd7, %rd2, %rd5; ; CHECK-NEXT: { ; CHECK-NEXT: .reg .b128 cmp, swap, dst; -; CHECK-NEXT: mov.b128 cmp, {%rd11, %rd12}; +; CHECK-NEXT: mov.b128 cmp, {%rd1, %rd2}; ; CHECK-NEXT: mov.b128 swap, {%rd6, %rd7}; ; CHECK-NEXT: atom.relaxed.sys.cas.b128 dst, [%rd3], cmp, swap; -; CHECK-NEXT: mov.b128 {%rd1, %rd2}, dst; +; CHECK-NEXT: mov.b128 {%rd11, %rd12}, dst; ; CHECK-NEXT: } -; CHECK-NEXT: xor.b64 %rd8, %rd2, %rd12; -; CHECK-NEXT: xor.b64 %rd9, %rd1, %rd11; +; CHECK-NEXT: xor.b64 %rd8, %rd12, %rd2; +; CHECK-NEXT: xor.b64 %rd9, %rd11, %rd1; ; CHECK-NEXT: or.b64 %rd10, %rd9, %rd8; ; CHECK-NEXT: setp.ne.b64 %p1, %rd10, 0; -; CHECK-NEXT: mov.b64 %rd11, %rd1; -; CHECK-NEXT: mov.b64 %rd12, %rd2; ; CHECK-NEXT: @%p1 bra $L__BB36_1; ; CHECK-NEXT: // %bb.2: // %atomicrmw.end -; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd1, %rd2}; +; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd11, %rd12}; ; CHECK-NEXT: ret; %ret = atomicrmw xor ptr %ptr, i128 %val monotonic ret i128 %ret @@ -861,29 +861,29 @@ define i128 @test_atomicrmw_min(ptr %ptr, i128 %val) { ; CHECK-NEXT: ld.v2.b64 {%rd11, %rd12}, [%rd3]; ; CHECK-NEXT: $L__BB37_1: // %atomicrmw.start ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: setp.lt.u64 %p1, %rd11, %rd4; -; CHECK-NEXT: setp.eq.b64 %p2, %rd12, %rd5; +; CHECK-NEXT: mov.b64 %rd2, %rd12; +; CHECK-NEXT: mov.b64 %rd1, %rd11; +; CHECK-NEXT: setp.lt.u64 %p1, %rd1, %rd4; +; CHECK-NEXT: setp.eq.b64 %p2, %rd2, %rd5; ; CHECK-NEXT: and.pred %p3, %p2, %p1; -; CHECK-NEXT: setp.lt.s64 %p4, %rd12, %rd5; +; CHECK-NEXT: setp.lt.s64 %p4, %rd2, %rd5; ; CHECK-NEXT: or.pred %p5, %p3, %p4; -; CHECK-NEXT: selp.b64 %rd6, %rd12, %rd5, %p5; -; CHECK-NEXT: selp.b64 %rd7, %rd11, %rd4, %p5; +; CHECK-NEXT: selp.b64 %rd6, %rd2, %rd5, %p5; +; CHECK-NEXT: selp.b64 %rd7, %rd1, %rd4, %p5; ; CHECK-NEXT: { ; CHECK-NEXT: .reg .b128 cmp, swap, dst; -; CHECK-NEXT: mov.b128 cmp, {%rd11, %rd12}; +; CHECK-NEXT: mov.b128 cmp, {%rd1, %rd2}; ; CHECK-NEXT: mov.b128 swap, {%rd7, %rd6}; ; CHECK-NEXT: atom.relaxed.sys.cas.b128 dst, [%rd3], cmp, swap; -; CHECK-NEXT: mov.b128 {%rd1, %rd2}, dst; +; CHECK-NEXT: mov.b128 {%rd11, %rd12}, dst; ; CHECK-NEXT: } -; CHECK-NEXT: xor.b64 %rd8, %rd2, %rd12; -; CHECK-NEXT: xor.b64 %rd9, %rd1, %rd11; +; CHECK-NEXT: xor.b64 %rd8, %rd12, %rd2; +; CHECK-NEXT: xor.b64 %rd9, %rd11, %rd1; ; CHECK-NEXT: or.b64 %rd10, %rd9, %rd8; ; CHECK-NEXT: setp.ne.b64 %p6, %rd10, 0; -; CHECK-NEXT: mov.b64 %rd11, %rd1; -; CHECK-NEXT: mov.b64 %rd12, %rd2; ; CHECK-NEXT: @%p6 bra $L__BB37_1; ; CHECK-NEXT: // %bb.2: // %atomicrmw.end -; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd1, %rd2}; +; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd11, %rd12}; ; CHECK-NEXT: ret; %ret = atomicrmw min ptr %ptr, i128 %val monotonic ret i128 %ret @@ -901,29 +901,29 @@ define i128 @test_atomicrmw_max(ptr %ptr, i128 %val) { ; CHECK-NEXT: ld.v2.b64 {%rd11, %rd12}, [%rd3]; ; CHECK-NEXT: $L__BB38_1: // %atomicrmw.start ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: setp.gt.u64 %p1, %rd11, %rd4; -; CHECK-NEXT: setp.eq.b64 %p2, %rd12, %rd5; +; CHECK-NEXT: mov.b64 %rd2, %rd12; +; CHECK-NEXT: mov.b64 %rd1, %rd11; +; CHECK-NEXT: setp.gt.u64 %p1, %rd1, %rd4; +; CHECK-NEXT: setp.eq.b64 %p2, %rd2, %rd5; ; CHECK-NEXT: and.pred %p3, %p2, %p1; -; CHECK-NEXT: setp.gt.s64 %p4, %rd12, %rd5; +; CHECK-NEXT: setp.gt.s64 %p4, %rd2, %rd5; ; CHECK-NEXT: or.pred %p5, %p3, %p4; -; CHECK-NEXT: selp.b64 %rd6, %rd12, %rd5, %p5; -; CHECK-NEXT: selp.b64 %rd7, %rd11, %rd4, %p5; +; CHECK-NEXT: selp.b64 %rd6, %rd2, %rd5, %p5; +; CHECK-NEXT: selp.b64 %rd7, %rd1, %rd4, %p5; ; CHECK-NEXT: { ; CHECK-NEXT: .reg .b128 cmp, swap, dst; -; CHECK-NEXT: mov.b128 cmp, {%rd11, %rd12}; +; CHECK-NEXT: mov.b128 cmp, {%rd1, %rd2}; ; CHECK-NEXT: mov.b128 swap, {%rd7, %rd6}; ; CHECK-NEXT: atom.relaxed.sys.cas.b128 dst, [%rd3], cmp, swap; -; CHECK-NEXT: mov.b128 {%rd1, %rd2}, dst; +; CHECK-NEXT: mov.b128 {%rd11, %rd12}, dst; ; CHECK-NEXT: } -; CHECK-NEXT: xor.b64 %rd8, %rd2, %rd12; -; CHECK-NEXT: xor.b64 %rd9, %rd1, %rd11; +; CHECK-NEXT: xor.b64 %rd8, %rd12, %rd2; +; CHECK-NEXT: xor.b64 %rd9, %rd11, %rd1; ; CHECK-NEXT: or.b64 %rd10, %rd9, %rd8; ; CHECK-NEXT: setp.ne.b64 %p6, %rd10, 0; -; CHECK-NEXT: mov.b64 %rd11, %rd1; -; CHECK-NEXT: mov.b64 %rd12, %rd2; ; CHECK-NEXT: @%p6 bra $L__BB38_1; ; CHECK-NEXT: // %bb.2: // %atomicrmw.end -; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd1, %rd2}; +; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd11, %rd12}; ; CHECK-NEXT: ret; %ret = atomicrmw max ptr %ptr, i128 %val monotonic ret i128 %ret @@ -941,29 +941,29 @@ define i128 @test_atomicrmw_umin(ptr %ptr, i128 %val) { ; CHECK-NEXT: ld.v2.b64 {%rd11, %rd12}, [%rd3]; ; CHECK-NEXT: $L__BB39_1: // %atomicrmw.start ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: setp.lt.u64 %p1, %rd11, %rd4; -; CHECK-NEXT: setp.eq.b64 %p2, %rd12, %rd5; +; CHECK-NEXT: mov.b64 %rd2, %rd12; +; CHECK-NEXT: mov.b64 %rd1, %rd11; +; CHECK-NEXT: setp.lt.u64 %p1, %rd1, %rd4; +; CHECK-NEXT: setp.eq.b64 %p2, %rd2, %rd5; ; CHECK-NEXT: and.pred %p3, %p2, %p1; -; CHECK-NEXT: setp.lt.u64 %p4, %rd12, %rd5; +; CHECK-NEXT: setp.lt.u64 %p4, %rd2, %rd5; ; CHECK-NEXT: or.pred %p5, %p3, %p4; -; CHECK-NEXT: selp.b64 %rd6, %rd12, %rd5, %p5; -; CHECK-NEXT: selp.b64 %rd7, %rd11, %rd4, %p5; +; CHECK-NEXT: selp.b64 %rd6, %rd2, %rd5, %p5; +; CHECK-NEXT: selp.b64 %rd7, %rd1, %rd4, %p5; ; CHECK-NEXT: { ; CHECK-NEXT: .reg .b128 cmp, swap, dst; -; CHECK-NEXT: mov.b128 cmp, {%rd11, %rd12}; +; CHECK-NEXT: mov.b128 cmp, {%rd1, %rd2}; ; CHECK-NEXT: mov.b128 swap, {%rd7, %rd6}; ; CHECK-NEXT: atom.relaxed.sys.cas.b128 dst, [%rd3], cmp, swap; -; CHECK-NEXT: mov.b128 {%rd1, %rd2}, dst; +; CHECK-NEXT: mov.b128 {%rd11, %rd12}, dst; ; CHECK-NEXT: } -; CHECK-NEXT: xor.b64 %rd8, %rd2, %rd12; -; CHECK-NEXT: xor.b64 %rd9, %rd1, %rd11; +; CHECK-NEXT: xor.b64 %rd8, %rd12, %rd2; +; CHECK-NEXT: xor.b64 %rd9, %rd11, %rd1; ; CHECK-NEXT: or.b64 %rd10, %rd9, %rd8; ; CHECK-NEXT: setp.ne.b64 %p6, %rd10, 0; -; CHECK-NEXT: mov.b64 %rd11, %rd1; -; CHECK-NEXT: mov.b64 %rd12, %rd2; ; CHECK-NEXT: @%p6 bra $L__BB39_1; ; CHECK-NEXT: // %bb.2: // %atomicrmw.end -; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd1, %rd2}; +; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd11, %rd12}; ; CHECK-NEXT: ret; %ret = atomicrmw umin ptr %ptr, i128 %val monotonic ret i128 %ret @@ -981,29 +981,29 @@ define i128 @test_atomicrmw_umax(ptr %ptr, i128 %val) { ; CHECK-NEXT: ld.v2.b64 {%rd11, %rd12}, [%rd3]; ; CHECK-NEXT: $L__BB40_1: // %atomicrmw.start ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: setp.gt.u64 %p1, %rd11, %rd4; -; CHECK-NEXT: setp.eq.b64 %p2, %rd12, %rd5; +; CHECK-NEXT: mov.b64 %rd2, %rd12; +; CHECK-NEXT: mov.b64 %rd1, %rd11; +; CHECK-NEXT: setp.gt.u64 %p1, %rd1, %rd4; +; CHECK-NEXT: setp.eq.b64 %p2, %rd2, %rd5; ; CHECK-NEXT: and.pred %p3, %p2, %p1; -; CHECK-NEXT: setp.gt.u64 %p4, %rd12, %rd5; +; CHECK-NEXT: setp.gt.u64 %p4, %rd2, %rd5; ; CHECK-NEXT: or.pred %p5, %p3, %p4; -; CHECK-NEXT: selp.b64 %rd6, %rd12, %rd5, %p5; -; CHECK-NEXT: selp.b64 %rd7, %rd11, %rd4, %p5; +; CHECK-NEXT: selp.b64 %rd6, %rd2, %rd5, %p5; +; CHECK-NEXT: selp.b64 %rd7, %rd1, %rd4, %p5; ; CHECK-NEXT: { ; CHECK-NEXT: .reg .b128 cmp, swap, dst; -; CHECK-NEXT: mov.b128 cmp, {%rd11, %rd12}; +; CHECK-NEXT: mov.b128 cmp, {%rd1, %rd2}; ; CHECK-NEXT: mov.b128 swap, {%rd7, %rd6}; ; CHECK-NEXT: atom.relaxed.sys.cas.b128 dst, [%rd3], cmp, swap; -; CHECK-NEXT: mov.b128 {%rd1, %rd2}, dst; +; CHECK-NEXT: mov.b128 {%rd11, %rd12}, dst; ; CHECK-NEXT: } -; CHECK-NEXT: xor.b64 %rd8, %rd2, %rd12; -; CHECK-NEXT: xor.b64 %rd9, %rd1, %rd11; +; CHECK-NEXT: xor.b64 %rd8, %rd12, %rd2; +; CHECK-NEXT: xor.b64 %rd9, %rd11, %rd1; ; CHECK-NEXT: or.b64 %rd10, %rd9, %rd8; ; CHECK-NEXT: setp.ne.b64 %p6, %rd10, 0; -; CHECK-NEXT: mov.b64 %rd11, %rd1; -; CHECK-NEXT: mov.b64 %rd12, %rd2; ; CHECK-NEXT: @%p6 bra $L__BB40_1; ; CHECK-NEXT: // %bb.2: // %atomicrmw.end -; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd1, %rd2}; +; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd11, %rd12}; ; CHECK-NEXT: ret; %ret = atomicrmw umax ptr %ptr, i128 %val monotonic ret i128 %ret diff --git a/llvm/test/CodeGen/NVPTX/atomics-sm70.ll b/llvm/test/CodeGen/NVPTX/atomics-sm70.ll index e2762bac45a35..313be95c03192 100644 --- a/llvm/test/CodeGen/NVPTX/atomics-sm70.ll +++ b/llvm/test/CodeGen/NVPTX/atomics-sm70.ll @@ -63,32 +63,32 @@ define void @test(ptr %dp0, ptr addrspace(1) %dp1, ptr addrspace(3) %dp3, half % ; CHECKPTX62-NEXT: ld.b32 %r46, [%r1]; ; CHECKPTX62-NEXT: $L__BB0_1: // %atomicrmw.start45 ; CHECKPTX62-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECKPTX62-NEXT: shr.u32 %r20, %r46, %r2; +; CHECKPTX62-NEXT: mov.b32 %r4, %r46; +; CHECKPTX62-NEXT: shr.u32 %r20, %r4, %r2; ; CHECKPTX62-NEXT: cvt.u16.u32 %rs2, %r20; ; CHECKPTX62-NEXT: add.rn.f16 %rs3, %rs2, %rs1; ; CHECKPTX62-NEXT: cvt.u32.u16 %r21, %rs3; ; CHECKPTX62-NEXT: shl.b32 %r22, %r21, %r2; -; CHECKPTX62-NEXT: and.b32 %r23, %r46, %r3; +; CHECKPTX62-NEXT: and.b32 %r23, %r4, %r3; ; CHECKPTX62-NEXT: or.b32 %r24, %r23, %r22; -; CHECKPTX62-NEXT: atom.relaxed.sys.cas.b32 %r4, [%r1], %r46, %r24; -; CHECKPTX62-NEXT: setp.ne.b32 %p1, %r4, %r46; -; CHECKPTX62-NEXT: mov.b32 %r46, %r4; +; CHECKPTX62-NEXT: atom.relaxed.sys.cas.b32 %r46, [%r1], %r4, %r24; +; CHECKPTX62-NEXT: setp.ne.b32 %p1, %r46, %r4; ; CHECKPTX62-NEXT: @%p1 bra $L__BB0_1; ; CHECKPTX62-NEXT: // %bb.2: // %atomicrmw.end44 ; CHECKPTX62-NEXT: ld.b32 %r47, [%r1]; ; CHECKPTX62-NEXT: $L__BB0_3: // %atomicrmw.start27 ; CHECKPTX62-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECKPTX62-NEXT: shr.u32 %r25, %r47, %r2; +; CHECKPTX62-NEXT: mov.b32 %r5, %r47; +; CHECKPTX62-NEXT: shr.u32 %r25, %r5, %r2; ; CHECKPTX62-NEXT: cvt.u16.u32 %rs4, %r25; ; CHECKPTX62-NEXT: mov.b16 %rs5, 0x3C00; ; CHECKPTX62-NEXT: add.rn.f16 %rs6, %rs4, %rs5; ; CHECKPTX62-NEXT: cvt.u32.u16 %r26, %rs6; ; CHECKPTX62-NEXT: shl.b32 %r27, %r26, %r2; -; CHECKPTX62-NEXT: and.b32 %r28, %r47, %r3; +; CHECKPTX62-NEXT: and.b32 %r28, %r5, %r3; ; CHECKPTX62-NEXT: or.b32 %r29, %r28, %r27; -; CHECKPTX62-NEXT: atom.relaxed.sys.cas.b32 %r5, [%r1], %r47, %r29; -; CHECKPTX62-NEXT: setp.ne.b32 %p2, %r5, %r47; -; CHECKPTX62-NEXT: mov.b32 %r47, %r5; +; CHECKPTX62-NEXT: atom.relaxed.sys.cas.b32 %r47, [%r1], %r5, %r29; +; CHECKPTX62-NEXT: setp.ne.b32 %p2, %r47, %r5; ; CHECKPTX62-NEXT: @%p2 bra $L__BB0_3; ; CHECKPTX62-NEXT: // %bb.4: // %atomicrmw.end26 ; CHECKPTX62-NEXT: and.b32 %r6, %r14, -4; @@ -100,16 +100,16 @@ define void @test(ptr %dp0, ptr addrspace(1) %dp1, ptr addrspace(3) %dp3, half % ; CHECKPTX62-NEXT: ld.global.b32 %r48, [%r6]; ; CHECKPTX62-NEXT: $L__BB0_5: // %atomicrmw.start9 ; CHECKPTX62-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECKPTX62-NEXT: shr.u32 %r33, %r48, %r7; +; CHECKPTX62-NEXT: mov.b32 %r9, %r48; +; CHECKPTX62-NEXT: shr.u32 %r33, %r9, %r7; ; CHECKPTX62-NEXT: cvt.u16.u32 %rs7, %r33; ; CHECKPTX62-NEXT: add.rn.f16 %rs8, %rs7, %rs1; ; CHECKPTX62-NEXT: cvt.u32.u16 %r34, %rs8; ; CHECKPTX62-NEXT: shl.b32 %r35, %r34, %r7; -; CHECKPTX62-NEXT: and.b32 %r36, %r48, %r8; +; CHECKPTX62-NEXT: and.b32 %r36, %r9, %r8; ; CHECKPTX62-NEXT: or.b32 %r37, %r36, %r35; -; CHECKPTX62-NEXT: atom.relaxed.sys.global.cas.b32 %r9, [%r6], %r48, %r37; -; CHECKPTX62-NEXT: setp.ne.b32 %p3, %r9, %r48; -; CHECKPTX62-NEXT: mov.b32 %r48, %r9; +; CHECKPTX62-NEXT: atom.relaxed.sys.global.cas.b32 %r48, [%r6], %r9, %r37; +; CHECKPTX62-NEXT: setp.ne.b32 %p3, %r48, %r9; ; CHECKPTX62-NEXT: @%p3 bra $L__BB0_5; ; CHECKPTX62-NEXT: // %bb.6: // %atomicrmw.end8 ; CHECKPTX62-NEXT: and.b32 %r10, %r15, -4; @@ -121,16 +121,16 @@ define void @test(ptr %dp0, ptr addrspace(1) %dp1, ptr addrspace(3) %dp3, half % ; CHECKPTX62-NEXT: ld.shared.b32 %r49, [%r10]; ; CHECKPTX62-NEXT: $L__BB0_7: // %atomicrmw.start ; CHECKPTX62-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECKPTX62-NEXT: shr.u32 %r41, %r49, %r11; +; CHECKPTX62-NEXT: mov.b32 %r13, %r49; +; CHECKPTX62-NEXT: shr.u32 %r41, %r13, %r11; ; CHECKPTX62-NEXT: cvt.u16.u32 %rs9, %r41; ; CHECKPTX62-NEXT: add.rn.f16 %rs10, %rs9, %rs1; ; CHECKPTX62-NEXT: cvt.u32.u16 %r42, %rs10; ; CHECKPTX62-NEXT: shl.b32 %r43, %r42, %r11; -; CHECKPTX62-NEXT: and.b32 %r44, %r49, %r12; +; CHECKPTX62-NEXT: and.b32 %r44, %r13, %r12; ; CHECKPTX62-NEXT: or.b32 %r45, %r44, %r43; -; CHECKPTX62-NEXT: atom.relaxed.sys.shared.cas.b32 %r13, [%r10], %r49, %r45; -; CHECKPTX62-NEXT: setp.ne.b32 %p4, %r13, %r49; -; CHECKPTX62-NEXT: mov.b32 %r49, %r13; +; CHECKPTX62-NEXT: atom.relaxed.sys.shared.cas.b32 %r49, [%r10], %r13, %r45; +; CHECKPTX62-NEXT: setp.ne.b32 %p4, %r49, %r13; ; CHECKPTX62-NEXT: @%p4 bra $L__BB0_7; ; CHECKPTX62-NEXT: // %bb.8: // %atomicrmw.end ; CHECKPTX62-NEXT: ret; diff --git a/llvm/test/CodeGen/NVPTX/atomics-sm90.ll b/llvm/test/CodeGen/NVPTX/atomics-sm90.ll index e6c6a73eef14d..f5eefaa57fc09 100644 --- a/llvm/test/CodeGen/NVPTX/atomics-sm90.ll +++ b/llvm/test/CodeGen/NVPTX/atomics-sm90.ll @@ -63,33 +63,33 @@ define void @test(ptr %dp0, ptr addrspace(1) %dp1, ptr addrspace(3) %dp3, bfloat ; CHECKPTX71-NEXT: ld.b32 %r46, [%r1]; ; CHECKPTX71-NEXT: $L__BB0_1: // %atomicrmw.start45 ; CHECKPTX71-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECKPTX71-NEXT: shr.u32 %r20, %r46, %r2; +; CHECKPTX71-NEXT: mov.b32 %r4, %r46; +; CHECKPTX71-NEXT: shr.u32 %r20, %r4, %r2; ; CHECKPTX71-NEXT: cvt.u16.u32 %rs2, %r20; ; CHECKPTX71-NEXT: mov.b16 %rs3, 0x3F80; ; CHECKPTX71-NEXT: fma.rn.bf16 %rs4, %rs2, %rs3, %rs1; ; CHECKPTX71-NEXT: cvt.u32.u16 %r21, %rs4; ; CHECKPTX71-NEXT: shl.b32 %r22, %r21, %r2; -; CHECKPTX71-NEXT: and.b32 %r23, %r46, %r3; +; CHECKPTX71-NEXT: and.b32 %r23, %r4, %r3; ; CHECKPTX71-NEXT: or.b32 %r24, %r23, %r22; -; CHECKPTX71-NEXT: atom.relaxed.sys.cas.b32 %r4, [%r1], %r46, %r24; -; CHECKPTX71-NEXT: setp.ne.b32 %p1, %r4, %r46; -; CHECKPTX71-NEXT: mov.b32 %r46, %r4; +; CHECKPTX71-NEXT: atom.relaxed.sys.cas.b32 %r46, [%r1], %r4, %r24; +; CHECKPTX71-NEXT: setp.ne.b32 %p1, %r46, %r4; ; CHECKPTX71-NEXT: @%p1 bra $L__BB0_1; ; CHECKPTX71-NEXT: // %bb.2: // %atomicrmw.end44 ; CHECKPTX71-NEXT: ld.b32 %r47, [%r1]; ; CHECKPTX71-NEXT: $L__BB0_3: // %atomicrmw.start27 ; CHECKPTX71-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECKPTX71-NEXT: shr.u32 %r25, %r47, %r2; +; CHECKPTX71-NEXT: mov.b32 %r5, %r47; +; CHECKPTX71-NEXT: shr.u32 %r25, %r5, %r2; ; CHECKPTX71-NEXT: cvt.u16.u32 %rs5, %r25; ; CHECKPTX71-NEXT: mov.b16 %rs6, 0x3F80; ; CHECKPTX71-NEXT: fma.rn.bf16 %rs7, %rs5, %rs6, %rs6; ; CHECKPTX71-NEXT: cvt.u32.u16 %r26, %rs7; ; CHECKPTX71-NEXT: shl.b32 %r27, %r26, %r2; -; CHECKPTX71-NEXT: and.b32 %r28, %r47, %r3; +; CHECKPTX71-NEXT: and.b32 %r28, %r5, %r3; ; CHECKPTX71-NEXT: or.b32 %r29, %r28, %r27; -; CHECKPTX71-NEXT: atom.relaxed.sys.cas.b32 %r5, [%r1], %r47, %r29; -; CHECKPTX71-NEXT: setp.ne.b32 %p2, %r5, %r47; -; CHECKPTX71-NEXT: mov.b32 %r47, %r5; +; CHECKPTX71-NEXT: atom.relaxed.sys.cas.b32 %r47, [%r1], %r5, %r29; +; CHECKPTX71-NEXT: setp.ne.b32 %p2, %r47, %r5; ; CHECKPTX71-NEXT: @%p2 bra $L__BB0_3; ; CHECKPTX71-NEXT: // %bb.4: // %atomicrmw.end26 ; CHECKPTX71-NEXT: and.b32 %r6, %r14, -4; @@ -101,17 +101,17 @@ define void @test(ptr %dp0, ptr addrspace(1) %dp1, ptr addrspace(3) %dp3, bfloat ; CHECKPTX71-NEXT: ld.global.b32 %r48, [%r6]; ; CHECKPTX71-NEXT: $L__BB0_5: // %atomicrmw.start9 ; CHECKPTX71-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECKPTX71-NEXT: shr.u32 %r33, %r48, %r7; +; CHECKPTX71-NEXT: mov.b32 %r9, %r48; +; CHECKPTX71-NEXT: shr.u32 %r33, %r9, %r7; ; CHECKPTX71-NEXT: cvt.u16.u32 %rs8, %r33; ; CHECKPTX71-NEXT: mov.b16 %rs9, 0x3F80; ; CHECKPTX71-NEXT: fma.rn.bf16 %rs10, %rs8, %rs9, %rs1; ; CHECKPTX71-NEXT: cvt.u32.u16 %r34, %rs10; ; CHECKPTX71-NEXT: shl.b32 %r35, %r34, %r7; -; CHECKPTX71-NEXT: and.b32 %r36, %r48, %r8; +; CHECKPTX71-NEXT: and.b32 %r36, %r9, %r8; ; CHECKPTX71-NEXT: or.b32 %r37, %r36, %r35; -; CHECKPTX71-NEXT: atom.relaxed.sys.global.cas.b32 %r9, [%r6], %r48, %r37; -; CHECKPTX71-NEXT: setp.ne.b32 %p3, %r9, %r48; -; CHECKPTX71-NEXT: mov.b32 %r48, %r9; +; CHECKPTX71-NEXT: atom.relaxed.sys.global.cas.b32 %r48, [%r6], %r9, %r37; +; CHECKPTX71-NEXT: setp.ne.b32 %p3, %r48, %r9; ; CHECKPTX71-NEXT: @%p3 bra $L__BB0_5; ; CHECKPTX71-NEXT: // %bb.6: // %atomicrmw.end8 ; CHECKPTX71-NEXT: and.b32 %r10, %r15, -4; @@ -123,17 +123,17 @@ define void @test(ptr %dp0, ptr addrspace(1) %dp1, ptr addrspace(3) %dp3, bfloat ; CHECKPTX71-NEXT: ld.shared.b32 %r49, [%r10]; ; CHECKPTX71-NEXT: $L__BB0_7: // %atomicrmw.start ; CHECKPTX71-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECKPTX71-NEXT: shr.u32 %r41, %r49, %r11; +; CHECKPTX71-NEXT: mov.b32 %r13, %r49; +; CHECKPTX71-NEXT: shr.u32 %r41, %r13, %r11; ; CHECKPTX71-NEXT: cvt.u16.u32 %rs11, %r41; ; CHECKPTX71-NEXT: mov.b16 %rs12, 0x3F80; ; CHECKPTX71-NEXT: fma.rn.bf16 %rs13, %rs11, %rs12, %rs1; ; CHECKPTX71-NEXT: cvt.u32.u16 %r42, %rs13; ; CHECKPTX71-NEXT: shl.b32 %r43, %r42, %r11; -; CHECKPTX71-NEXT: and.b32 %r44, %r49, %r12; +; CHECKPTX71-NEXT: and.b32 %r44, %r13, %r12; ; CHECKPTX71-NEXT: or.b32 %r45, %r44, %r43; -; CHECKPTX71-NEXT: atom.relaxed.sys.shared.cas.b32 %r13, [%r10], %r49, %r45; -; CHECKPTX71-NEXT: setp.ne.b32 %p4, %r13, %r49; -; CHECKPTX71-NEXT: mov.b32 %r49, %r13; +; CHECKPTX71-NEXT: atom.relaxed.sys.shared.cas.b32 %r49, [%r10], %r13, %r45; +; CHECKPTX71-NEXT: setp.ne.b32 %p4, %r49, %r13; ; CHECKPTX71-NEXT: @%p4 bra $L__BB0_7; ; CHECKPTX71-NEXT: // %bb.8: // %atomicrmw.end ; CHECKPTX71-NEXT: ret; diff --git a/llvm/test/CodeGen/NVPTX/atomics.ll b/llvm/test/CodeGen/NVPTX/atomics.ll index 6ea02f35e9626..a4b49f7136d1d 100644 --- a/llvm/test/CodeGen/NVPTX/atomics.ll +++ b/llvm/test/CodeGen/NVPTX/atomics.ll @@ -442,22 +442,22 @@ define half @atomicrmw_add_f16_generic(ptr %addr, half %val) { ; CHECK-NEXT: cvt.f32.f16 %r10, %rs1; ; CHECK-NEXT: $L__BB24_1: // %atomicrmw.start ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: shr.u32 %r8, %r17, %r1; +; CHECK-NEXT: mov.b32 %r3, %r17; +; CHECK-NEXT: shr.u32 %r8, %r3, %r1; ; CHECK-NEXT: cvt.u16.u32 %rs2, %r8; ; CHECK-NEXT: cvt.f32.f16 %r9, %rs2; ; CHECK-NEXT: add.rn.f32 %r11, %r9, %r10; ; CHECK-NEXT: cvt.rn.f16.f32 %rs3, %r11; ; CHECK-NEXT: cvt.u32.u16 %r12, %rs3; ; CHECK-NEXT: shl.b32 %r13, %r12, %r1; -; CHECK-NEXT: and.b32 %r14, %r17, %r2; +; CHECK-NEXT: and.b32 %r14, %r3, %r2; ; CHECK-NEXT: or.b32 %r15, %r14, %r13; ; CHECK-NEXT: membar.sys; -; CHECK-NEXT: atom.cas.b32 %r3, [%rd1], %r17, %r15; -; CHECK-NEXT: setp.ne.b32 %p1, %r3, %r17; -; CHECK-NEXT: mov.b32 %r17, %r3; +; CHECK-NEXT: atom.cas.b32 %r17, [%rd1], %r3, %r15; +; CHECK-NEXT: setp.ne.b32 %p1, %r17, %r3; ; CHECK-NEXT: @%p1 bra $L__BB24_1; ; CHECK-NEXT: // %bb.2: // %atomicrmw.end -; CHECK-NEXT: shr.u32 %r16, %r3, %r1; +; CHECK-NEXT: shr.u32 %r16, %r17, %r1; ; CHECK-NEXT: st.param.b16 [func_retval0], %r16; ; CHECK-NEXT: ret; %ret = atomicrmw fadd ptr %addr, half %val seq_cst diff --git a/llvm/test/CodeGen/PowerPC/ctrloop-fp128.ll b/llvm/test/CodeGen/PowerPC/ctrloop-fp128.ll index d6dd959365401..fdb01314a7d4c 100644 --- a/llvm/test/CodeGen/PowerPC/ctrloop-fp128.ll +++ b/llvm/test/CodeGen/PowerPC/ctrloop-fp128.ll @@ -49,15 +49,15 @@ define void @fmul_ctrloop_fp128() nounwind { ; PWR8-NEXT: # ; PWR8-NEXT: lxvd2x 0, 30, 28 ; PWR8-NEXT: vmr 2, 31 -; PWR8-NEXT: addi 26, 30, 16 +; PWR8-NEXT: mr 26, 30 +; PWR8-NEXT: addi 30, 30, 16 ; PWR8-NEXT: xxswapd 35, 0 ; PWR8-NEXT: bl __mulkf3 ; PWR8-NEXT: nop ; PWR8-NEXT: addi 29, 29, -1 ; PWR8-NEXT: xxswapd 0, 34 ; PWR8-NEXT: cmpldi 29, 0 -; PWR8-NEXT: stxvd2x 0, 30, 27 -; PWR8-NEXT: mr 30, 26 +; PWR8-NEXT: stxvd2x 0, 26, 27 ; PWR8-NEXT: bc 12, 1, .LBB0_1 ; PWR8-NEXT: # %bb.2: # %for.end ; PWR8-NEXT: li 3, 48 diff --git a/llvm/test/CodeGen/PowerPC/licm-xxsplti.ll b/llvm/test/CodeGen/PowerPC/licm-xxsplti.ll index 55482a0c5ff2c..786988fae08c8 100644 --- a/llvm/test/CodeGen/PowerPC/licm-xxsplti.ll +++ b/llvm/test/CodeGen/PowerPC/licm-xxsplti.ll @@ -23,11 +23,11 @@ define void @_Z3fooPfS_Pi(ptr noalias nocapture noundef %_a, ptr noalias nocaptu ; AIX64-NEXT: # %bb.2: # %for.body.preheader.new ; AIX64-NEXT: rlwinm 6, 5, 0, 1, 30 ; AIX64-NEXT: xxspltib 0, 6 -; AIX64-NEXT: addi 9, 4, -8 +; AIX64-NEXT: addi 11, 4, -8 ; AIX64-NEXT: addi 7, 3, -8 ; AIX64-NEXT: li 8, 8 -; AIX64-NEXT: li 10, 12 -; AIX64-NEXT: li 11, 4 +; AIX64-NEXT: li 9, 12 +; AIX64-NEXT: li 10, 4 ; AIX64-NEXT: addi 6, 6, -2 ; AIX64-NEXT: rldicl 6, 6, 63, 1 ; AIX64-NEXT: addi 6, 6, 1 @@ -36,16 +36,16 @@ define void @_Z3fooPfS_Pi(ptr noalias nocapture noundef %_a, ptr noalias nocaptu ; AIX64-NEXT: .align 4 ; AIX64-NEXT: L..BB0_3: # %for.body ; AIX64-NEXT: # -; AIX64-NEXT: lxvwsx 1, 9, 8 +; AIX64-NEXT: lxvwsx 1, 11, 8 ; AIX64-NEXT: addi 6, 6, 2 ; AIX64-NEXT: xxland 1, 1, 0 ; AIX64-NEXT: xscvspdpn 1, 1 ; AIX64-NEXT: stfsu 1, 8(7) -; AIX64-NEXT: lxvwsx 1, 9, 10 -; AIX64-NEXT: addi 9, 9, 8 +; AIX64-NEXT: lxvwsx 1, 11, 9 +; AIX64-NEXT: addi 11, 11, 8 ; AIX64-NEXT: xxland 1, 1, 0 ; AIX64-NEXT: xxsldwi 1, 1, 1, 3 -; AIX64-NEXT: stfiwx 1, 7, 11 +; AIX64-NEXT: stfiwx 1, 7, 10 ; AIX64-NEXT: bdnz L..BB0_3 ; AIX64-NEXT: L..BB0_4: # %for.cond.cleanup.loopexit.unr-lcssa ; AIX64-NEXT: andi. 5, 5, 1 @@ -70,27 +70,27 @@ define void @_Z3fooPfS_Pi(ptr noalias nocapture noundef %_a, ptr noalias nocaptu ; AIX32-NEXT: # %bb.2: # %for.body.preheader.new ; AIX32-NEXT: xxspltib 0, 6 ; AIX32-NEXT: addi 12, 4, -8 -; AIX32-NEXT: addi 9, 3, -8 +; AIX32-NEXT: addi 8, 3, -8 ; AIX32-NEXT: rlwinm 7, 5, 0, 1, 30 -; AIX32-NEXT: li 8, 0 -; AIX32-NEXT: li 10, 8 -; AIX32-NEXT: li 11, 12 +; AIX32-NEXT: li 9, 8 +; AIX32-NEXT: li 10, 12 +; AIX32-NEXT: li 11, 0 ; AIX32-NEXT: .align 4 ; AIX32-NEXT: L..BB0_3: # %for.body ; AIX32-NEXT: # -; AIX32-NEXT: lxvwsx 1, 12, 10 +; AIX32-NEXT: lxvwsx 1, 12, 9 +; AIX32-NEXT: lxvwsx 2, 12, 10 ; AIX32-NEXT: addic 6, 6, 2 -; AIX32-NEXT: addze 8, 8 +; AIX32-NEXT: addi 12, 12, 8 +; AIX32-NEXT: addze 11, 11 ; AIX32-NEXT: xor 0, 6, 7 -; AIX32-NEXT: or. 0, 0, 8 +; AIX32-NEXT: or. 0, 0, 11 ; AIX32-NEXT: xxland 1, 1, 0 ; AIX32-NEXT: xscvspdpn 1, 1 -; AIX32-NEXT: stfsu 1, 8(9) -; AIX32-NEXT: lxvwsx 1, 12, 11 -; AIX32-NEXT: addi 12, 12, 8 -; AIX32-NEXT: xxland 1, 1, 0 +; AIX32-NEXT: stfsu 1, 8(8) +; AIX32-NEXT: xxland 1, 2, 0 ; AIX32-NEXT: xscvspdpn 1, 1 -; AIX32-NEXT: stfs 1, 4(9) +; AIX32-NEXT: stfs 1, 4(8) ; AIX32-NEXT: bne 0, L..BB0_3 ; AIX32-NEXT: L..BB0_4: # %for.cond.cleanup.loopexit.unr-lcssa ; AIX32-NEXT: andi. 5, 5, 1 @@ -116,11 +116,11 @@ define void @_Z3fooPfS_Pi(ptr noalias nocapture noundef %_a, ptr noalias nocaptu ; LINUX64LE-NEXT: # %bb.2: # %for.body.preheader.new ; LINUX64LE-NEXT: rlwinm 6, 5, 0, 1, 30 ; LINUX64LE-NEXT: xxspltib 0, 6 -; LINUX64LE-NEXT: addi 8, 4, -8 +; LINUX64LE-NEXT: addi 11, 4, -8 ; LINUX64LE-NEXT: addi 7, 3, -8 -; LINUX64LE-NEXT: li 9, 8 -; LINUX64LE-NEXT: li 10, 12 -; LINUX64LE-NEXT: li 11, 4 +; LINUX64LE-NEXT: li 8, 8 +; LINUX64LE-NEXT: li 9, 12 +; LINUX64LE-NEXT: li 10, 4 ; LINUX64LE-NEXT: addi 6, 6, -2 ; LINUX64LE-NEXT: rldicl 6, 6, 63, 1 ; LINUX64LE-NEXT: addi 6, 6, 1 @@ -129,16 +129,16 @@ define void @_Z3fooPfS_Pi(ptr noalias nocapture noundef %_a, ptr noalias nocaptu ; LINUX64LE-NEXT: .p2align 4 ; LINUX64LE-NEXT: .LBB0_3: # %for.body ; LINUX64LE-NEXT: # -; LINUX64LE-NEXT: lxvwsx 1, 8, 9 +; LINUX64LE-NEXT: lxvwsx 1, 11, 8 ; LINUX64LE-NEXT: addi 6, 6, 2 ; LINUX64LE-NEXT: xxland 1, 1, 0 ; LINUX64LE-NEXT: xxsldwi 1, 1, 1, 3 ; LINUX64LE-NEXT: xscvspdpn 1, 1 ; LINUX64LE-NEXT: stfsu 1, 8(7) -; LINUX64LE-NEXT: lxvwsx 1, 8, 10 -; LINUX64LE-NEXT: addi 8, 8, 8 +; LINUX64LE-NEXT: lxvwsx 1, 11, 9 +; LINUX64LE-NEXT: addi 11, 11, 8 ; LINUX64LE-NEXT: xxland 1, 1, 0 -; LINUX64LE-NEXT: stxvrwx 1, 7, 11 +; LINUX64LE-NEXT: stxvrwx 1, 7, 10 ; LINUX64LE-NEXT: bdnz .LBB0_3 ; LINUX64LE-NEXT: .LBB0_4: # %for.cond.cleanup.loopexit.unr-lcssa ; LINUX64LE-NEXT: andi. 5, 5, 1 diff --git a/llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll b/llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll index cc38e250f183f..4e0394ee4fb8c 100644 --- a/llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll +++ b/llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll @@ -189,8 +189,8 @@ define i64 @test_max_number_reminder(ptr %arg, i32 signext %arg1) { ; CHECK-NEXT: cmplwi r4, 0 ; CHECK-NEXT: beq cr0, .LBB2_4 ; CHECK-NEXT: # %bb.1: # %bb3.preheader -; CHECK-NEXT: std r25, -56(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r26, -48(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r27, -40(r1) # 8-byte Folded Spill ; CHECK-NEXT: addi r10, r3, 4002 ; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: li r5, -1 @@ -198,7 +198,6 @@ define i64 @test_max_number_reminder(ptr %arg, i32 signext %arg1) { ; CHECK-NEXT: li r7, 3 ; CHECK-NEXT: li r8, 5 ; CHECK-NEXT: li r9, 9 -; CHECK-NEXT: std r27, -40(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r28, -32(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill @@ -215,7 +214,7 @@ define i64 @test_max_number_reminder(ptr %arg, i32 signext %arg1) { ; CHECK-NEXT: ldx r28, r10, r8 ; CHECK-NEXT: ld r27, 12(r10) ; CHECK-NEXT: ld r26, 8(r10) -; CHECK-NEXT: ldx r25, r10, r9 +; CHECK-NEXT: ldx r12, r10, r9 ; CHECK-NEXT: addi r10, r10, 1 ; CHECK-NEXT: mulld r11, r11, r0 ; CHECK-NEXT: mulld r11, r11, r30 @@ -223,7 +222,7 @@ define i64 @test_max_number_reminder(ptr %arg, i32 signext %arg1) { ; CHECK-NEXT: mulld r11, r11, r28 ; CHECK-NEXT: mulld r11, r11, r27 ; CHECK-NEXT: mulld r11, r11, r26 -; CHECK-NEXT: maddld r3, r11, r25, r3 +; CHECK-NEXT: maddld r3, r11, r12, r3 ; CHECK-NEXT: bdnz .LBB2_2 ; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload @@ -232,7 +231,6 @@ define i64 @test_max_number_reminder(ptr %arg, i32 signext %arg1) { ; CHECK-NEXT: ld r27, -40(r1) # 8-byte Folded Reload ; CHECK-NEXT: add r3, r3, r4 ; CHECK-NEXT: ld r26, -48(r1) # 8-byte Folded Reload -; CHECK-NEXT: ld r25, -56(r1) # 8-byte Folded Reload ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB2_4: ; CHECK-NEXT: addi r3, r4, 0 diff --git a/llvm/test/CodeGen/PowerPC/perfect-shuffle.ll b/llvm/test/CodeGen/PowerPC/perfect-shuffle.ll index 7d6117719da1d..2f7d227fa9e06 100644 --- a/llvm/test/CodeGen/PowerPC/perfect-shuffle.ll +++ b/llvm/test/CodeGen/PowerPC/perfect-shuffle.ll @@ -162,16 +162,16 @@ define <4 x float> @shuffle5(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3, <16 x ; BE-ENABLE-NEXT: vextublx 3, 3, 2 ; BE-ENABLE-NEXT: xxmrghw 0, 1, 0 ; BE-ENABLE-NEXT: andi. 3, 3, 255 -; BE-ENABLE-NEXT: xxlor 1, 0, 0 +; BE-ENABLE-NEXT: xxlor 35, 0, 0 ; BE-ENABLE-NEXT: beq 0, .LBB4_2 ; BE-ENABLE-NEXT: # %bb.1: # %exit -; BE-ENABLE-NEXT: xvaddsp 34, 0, 1 +; BE-ENABLE-NEXT: xvaddsp 34, 35, 0 ; BE-ENABLE-NEXT: blr ; BE-ENABLE-NEXT: .LBB4_2: # %second -; BE-ENABLE-NEXT: xxmrglw 1, 36, 37 -; BE-ENABLE-NEXT: xxmrghw 2, 36, 37 -; BE-ENABLE-NEXT: xxmrghw 1, 2, 1 -; BE-ENABLE-NEXT: xvaddsp 34, 0, 1 +; BE-ENABLE-NEXT: xxmrglw 0, 36, 37 +; BE-ENABLE-NEXT: xxmrghw 1, 36, 37 +; BE-ENABLE-NEXT: xxmrghw 0, 1, 0 +; BE-ENABLE-NEXT: xvaddsp 34, 35, 0 ; BE-ENABLE-NEXT: blr entry: %shuf1 = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19, i32 24, i32 25, i32 26, i32 27> diff --git a/llvm/test/CodeGen/PowerPC/sms-phi-1.ll b/llvm/test/CodeGen/PowerPC/sms-phi-1.ll index 516d54ba2fdbe..509457042ed68 100644 --- a/llvm/test/CodeGen/PowerPC/sms-phi-1.ll +++ b/llvm/test/CodeGen/PowerPC/sms-phi-1.ll @@ -26,11 +26,12 @@ define void @main() nounwind #0 { ; CHECK-NEXT: mullw 4, 6, 6 ; CHECK-NEXT: addi 5, 6, 1 ; CHECK-NEXT: bdz .LBB0_3 -; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .LBB0_2: +; CHECK-NEXT: mr 6, 5 ; CHECK-NEXT: stwu 4, 4(3) -; CHECK-NEXT: mullw 4, 5, 5 ; CHECK-NEXT: addi 5, 5, 1 +; CHECK-NEXT: mullw 4, 6, 6 ; CHECK-NEXT: bdnz .LBB0_2 ; CHECK-NEXT: .LBB0_3: ; CHECK-NEXT: stwu 4, 4(3) diff --git a/llvm/test/CodeGen/PowerPC/sms-phi-2.ll b/llvm/test/CodeGen/PowerPC/sms-phi-2.ll index 4904d11fc8104..8b4b50239a1a0 100644 --- a/llvm/test/CodeGen/PowerPC/sms-phi-2.ll +++ b/llvm/test/CodeGen/PowerPC/sms-phi-2.ll @@ -5,46 +5,45 @@ define void @phi2(i32, i32, ptr) local_unnamed_addr { ; CHECK-LABEL: phi2: ; CHECK: # %bb.0: -; CHECK-NEXT: divw 8, 3, 4 +; CHECK-NEXT: divw 7, 3, 4 ; CHECK-NEXT: li 5, 55 ; CHECK-NEXT: li 6, 48 ; CHECK-NEXT: mtctr 3 ; CHECK-NEXT: bdz .LBB0_4 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: divw 9, 8, 4 -; CHECK-NEXT: mullw 7, 8, 4 -; CHECK-NEXT: sub 3, 3, 7 +; CHECK-NEXT: divw 9, 7, 4 +; CHECK-NEXT: mullw 8, 7, 4 +; CHECK-NEXT: sub 3, 3, 8 ; CHECK-NEXT: cmplwi 3, 10 -; CHECK-NEXT: isellt 7, 6, 5 -; CHECK-NEXT: add 3, 7, 3 -; CHECK-NEXT: stbu 3, -1(7) -; CHECK-NEXT: mr 3, 8 +; CHECK-NEXT: isellt 8, 6, 5 +; CHECK-NEXT: add 3, 8, 3 +; CHECK-NEXT: stbu 3, -1(8) ; CHECK-NEXT: bdz .LBB0_3 ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB0_2: -; CHECK-NEXT: mr 3, 9 -; CHECK-NEXT: mullw 9, 9, 4 -; CHECK-NEXT: divw 10, 3, 4 -; CHECK-NEXT: sub 8, 8, 9 -; CHECK-NEXT: cmplwi 8, 10 -; CHECK-NEXT: isellt 9, 6, 5 -; CHECK-NEXT: add 8, 9, 8 -; CHECK-NEXT: mr 9, 10 -; CHECK-NEXT: stbu 8, -1(7) -; CHECK-NEXT: mr 8, 3 +; CHECK-NEXT: mr 3, 7 +; CHECK-NEXT: mr 7, 9 +; CHECK-NEXT: mullw 10, 9, 4 +; CHECK-NEXT: divw 9, 9, 4 +; CHECK-NEXT: sub 3, 3, 10 +; CHECK-NEXT: cmplwi 3, 10 +; CHECK-NEXT: isellt 10, 6, 5 +; CHECK-NEXT: add 3, 10, 3 +; CHECK-NEXT: stbu 3, -1(8) ; CHECK-NEXT: bdnz .LBB0_2 ; CHECK-NEXT: .LBB0_3: -; CHECK-NEXT: mr 8, 9 +; CHECK-NEXT: mr 3, 7 +; CHECK-NEXT: mr 7, 9 ; CHECK-NEXT: b .LBB0_5 ; CHECK-NEXT: .LBB0_4: -; CHECK-NEXT: # implicit-def: $x7 +; CHECK-NEXT: # implicit-def: $x8 ; CHECK-NEXT: .LBB0_5: -; CHECK-NEXT: mullw 4, 8, 4 +; CHECK-NEXT: mullw 4, 7, 4 ; CHECK-NEXT: sub 3, 3, 4 ; CHECK-NEXT: cmplwi 3, 10 ; CHECK-NEXT: isellt 4, 6, 5 ; CHECK-NEXT: add 3, 4, 3 -; CHECK-NEXT: stbu 3, -1(7) +; CHECK-NEXT: stbu 3, -1(8) ; CHECK-NEXT: blr br label %4 diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-fadd-01.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-fadd-01.ll index 1bfa055781c98..f77abd95f8e0f 100644 --- a/llvm/test/CodeGen/SystemZ/atomicrmw-fadd-01.ll +++ b/llvm/test/CodeGen/SystemZ/atomicrmw-fadd-01.ll @@ -6,14 +6,15 @@ define float @f1(ptr %src, float %b) { ; CHECK-LABEL: f1: ; CHECK: le [[F:%f[0-9]+]], 0(%r2) ; CHECK: [[L:\.L.+]]: -; CHECK: lgdr [[RI:%r[0-9]+]], [[F]] -; CHECK: aebr [[F]], %f0 -; CHECK: lgdr [[RO:%r[0-9]+]], [[F]] +; CHECK: ler [[COPY_F:%f[0-9]+]], [[F]] +; CHECK-NEXT: aebr [[F]], %f0 +; CHECK-NEXT: lgdr [[RO:%r[0-9]+]], [[F]] ; CHECK: srlg [[RO]], [[RO]], 32 +; CHECK: lgdr [[RI:%r[0-9]+]], [[COPY_F]] ; CHECK: srlg [[RI]], [[RI]], 32 ; CHECK: cs [[RI]], [[RO]], 0(%r2) -; CHECK: sllg [[RI]], [[RI]], 32 -; CHECK: ldgr [[F]], [[RI]] +; CHECK: sllg [[RO]], [[RI]], 32 +; CHECK: ldgr [[F]], [[RO]] ; CHECK: jl [[L]] ; CHECK: ler %f0, [[F]] ; CHECK: br %r14 diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-fsub-01.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-fsub-01.ll index 3f4ad31762753..ffe25694885a9 100644 --- a/llvm/test/CodeGen/SystemZ/atomicrmw-fsub-01.ll +++ b/llvm/test/CodeGen/SystemZ/atomicrmw-fsub-01.ll @@ -6,14 +6,15 @@ define float @f1(ptr %src, float %b) { ; CHECK-LABEL: f1: ; CHECK: le [[F:%f[0-9]+]], 0(%r2) ; CHECK: [[L:\.L.+]]: -; CHECK: lgdr [[RI:%r[0-9]+]], [[F]] -; CHECK: sebr [[F]], %f0 -; CHECK: lgdr [[RO:%r[0-9]+]], [[F]] +; CHECK: ler [[COPY_F:%f[0-9]+]], [[F]] +; CHECK-NEXT: sebr [[F]], %f0 +; CHECK-NEXT: lgdr [[RO:%r[0-9]+]], [[F]] ; CHECK: srlg [[RO]], [[RO]], 32 +; CHECK: lgdr [[RI:%r[0-9]+]], [[COPY_F]] ; CHECK: srlg [[RI]], [[RI]], 32 ; CHECK: cs [[RI]], [[RO]], 0(%r2) -; CHECK: sllg [[RI]], [[RI]], 32 -; CHECK: ldgr [[F]], [[RI]] +; CHECK: sllg [[RO]], [[RI]], 32 +; CHECK: ldgr [[F]], [[RO]] ; CHECK: jl [[L]] ; CHECK: ler %f0, [[F]] ; CHECK: br %r14 diff --git a/llvm/test/CodeGen/WebAssembly/simd-shift-in-loop.ll b/llvm/test/CodeGen/WebAssembly/simd-shift-in-loop.ll index 75612ba645ca4..9e4faa96dbf26 100644 --- a/llvm/test/CodeGen/WebAssembly/simd-shift-in-loop.ll +++ b/llvm/test/CodeGen/WebAssembly/simd-shift-in-loop.ll @@ -15,16 +15,15 @@ define void @shl_loop(ptr %a, i8 %shift, i32 %count) { ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: loop # label0: ; CHECK-NEXT: local.get 0 +; CHECK-NEXT: local.tee 3 ; CHECK-NEXT: i32.const 16 ; CHECK-NEXT: i32.add -; CHECK-NEXT: local.tee 3 -; CHECK-NEXT: local.get 0 +; CHECK-NEXT: local.tee 0 +; CHECK-NEXT: local.get 3 ; CHECK-NEXT: v128.load 0:p2align=0 ; CHECK-NEXT: local.get 1 ; CHECK-NEXT: i8x16.shl ; CHECK-NEXT: v128.store 0 -; CHECK-NEXT: local.get 3 -; CHECK-NEXT: local.set 0 ; CHECK-NEXT: local.get 2 ; CHECK-NEXT: i32.const -1 ; CHECK-NEXT: i32.add @@ -64,10 +63,11 @@ define void @shl_phi_loop(ptr %a, i8 %shift, i32 %count) { ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: loop # label1: ; CHECK-NEXT: local.get 0 +; CHECK-NEXT: local.tee 3 ; CHECK-NEXT: i32.const 16 ; CHECK-NEXT: i32.add -; CHECK-NEXT: local.tee 3 -; CHECK-NEXT: local.get 0 +; CHECK-NEXT: local.tee 0 +; CHECK-NEXT: local.get 3 ; CHECK-NEXT: v128.load 0:p2align=0 ; CHECK-NEXT: local.get 1 ; CHECK-NEXT: i8x16.shl @@ -76,8 +76,6 @@ define void @shl_phi_loop(ptr %a, i8 %shift, i32 %count) { ; CHECK-NEXT: i32.const 1 ; CHECK-NEXT: i32.and ; CHECK-NEXT: local.set 1 -; CHECK-NEXT: local.get 3 -; CHECK-NEXT: local.set 0 ; CHECK-NEXT: local.get 2 ; CHECK-NEXT: i32.const -1 ; CHECK-NEXT: i32.add _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
