llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-llvm-transforms Author: Mircea Trofin (mtrofin) <details> <summary>Changes</summary> --- Full diff: https://github.com/llvm/llvm-project/pull/170752.diff 3 Files Affected: - (modified) llvm/lib/Transforms/IPO/LowerTypeTests.cpp (+3) - (modified) llvm/test/Transforms/LowerTypeTests/import.ll (+14-7) - (modified) llvm/utils/profcheck-xfail.txt (-2) ``````````diff diff --git a/llvm/lib/Transforms/IPO/LowerTypeTests.cpp b/llvm/lib/Transforms/IPO/LowerTypeTests.cpp index f7aeda95e41b3..ef0bc29b03c2a 100644 --- a/llvm/lib/Transforms/IPO/LowerTypeTests.cpp +++ b/llvm/lib/Transforms/IPO/LowerTypeTests.cpp @@ -54,6 +54,7 @@ #include "llvm/IR/ModuleSummaryIndexYAML.h" #include "llvm/IR/Operator.h" #include "llvm/IR/PassManager.h" +#include "llvm/IR/ProfDataUtils.h" #include "llvm/IR/ReplaceConstant.h" #include "llvm/IR/Type.h" #include "llvm/IR/Use.h" @@ -803,6 +804,8 @@ Value *LowerTypeTestsModule::lowerTypeTestCall(Metadata *TypeId, CallInst *CI, } IRBuilder<> ThenB(SplitBlockAndInsertIfThen(OffsetInRange, CI, false)); + setExplicitlyUnknownBranchWeightsIfProfiled(*InitialBB->getTerminator(), + DEBUG_TYPE); // Now that we know that the offset is in range and aligned, load the // appropriate bit from the bitset. diff --git a/llvm/test/Transforms/LowerTypeTests/import.ll b/llvm/test/Transforms/LowerTypeTests/import.ll index 2aa81362415ef..7a6f863753f3c 100644 --- a/llvm/test/Transforms/LowerTypeTests/import.ll +++ b/llvm/test/Transforms/LowerTypeTests/import.ll @@ -86,14 +86,14 @@ define i1 @allones32(ptr %p) { ret i1 %x } -define i1 @bytearray7(ptr %p) { +define i1 @bytearray7(ptr %p) !prof !0 { ; X86-LABEL: define i1 @bytearray7( -; X86-SAME: ptr [[P:%.*]]) { +; X86-SAME: ptr [[P:%.*]]) !prof [[PROF6:![0-9]+]] { ; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64 ; X86-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_bytearray7_global_addr to i64), [[TMP1]] ; X86-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_bytearray7_align to i64)) ; X86-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_bytearray7_size_m1 to i64) -; X86-NEXT: br i1 [[TMP8]], label [[TMP5:%.*]], label [[TMP14:%.*]] +; X86-NEXT: br i1 [[TMP8]], label [[TMP5:%.*]], label [[TMP14:%.*]], !prof [[PROF7:![0-9]+]] ; X86: 5: ; X86-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr @__typeid_bytearray7_byte_array, i64 [[TMP7]] ; X86-NEXT: [[TMP11:%.*]] = load i8, ptr [[TMP10]], align 1 @@ -105,12 +105,12 @@ define i1 @bytearray7(ptr %p) { ; X86-NEXT: ret i1 [[TMP15]] ; ; ARM-LABEL: define i1 @bytearray7( -; ARM-SAME: ptr [[P:%.*]]) { +; ARM-SAME: ptr [[P:%.*]]) !prof [[PROF0:![0-9]+]] { ; ARM-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64 ; ARM-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_bytearray7_global_addr to i64), [[TMP1]] ; ARM-NEXT: [[TMP5:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 3) ; ARM-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], 43 -; ARM-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP12:%.*]] +; ARM-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP12:%.*]], !prof [[PROF1:![0-9]+]] ; ARM: 5: ; ARM-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr @__typeid_bytearray7_byte_array, i64 [[TMP5]] ; ARM-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1 @@ -255,6 +255,8 @@ define i1 @single(ptr %p) { ret i1 %x } +!0 = !{!"function_entry_count", i32 10} + ; X86: !0 = !{i64 0, i64 256} ; X86: !1 = !{i64 0, i64 64} ; X86: !2 = !{i64 -1, i64 -1} @@ -265,13 +267,18 @@ define i1 @single(ptr %p) { ; X86: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } ; X86: attributes #[[ATTR1:[0-9]+]] = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } ;. +; ARM: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +; ARM: attributes #[[ATTR1:[0-9]+]] = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } +;. ; X86: [[META0]] = !{i64 0, i64 256} ; X86: [[META1]] = !{i64 0, i64 64} ; X86: [[META2]] = !{i64 -1, i64 -1} ; X86: [[META3]] = !{i64 0, i64 32} ; X86: [[META4]] = !{i64 0, i64 4294967296} ; X86: [[META5]] = !{i64 0, i64 128} +; X86: [[PROF6]] = !{!"function_entry_count", i32 10} +; X86: [[PROF7]] = !{!"unknown", !"lowertypetests"} ;. -; ARM: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -; ARM: attributes #[[ATTR1:[0-9]+]] = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } +; ARM: [[PROF0]] = !{!"function_entry_count", i32 10} +; ARM: [[PROF1]] = !{!"unknown", !"lowertypetests"} ;. diff --git a/llvm/utils/profcheck-xfail.txt b/llvm/utils/profcheck-xfail.txt index 3cde50de7d0c1..a36cec940b605 100644 --- a/llvm/utils/profcheck-xfail.txt +++ b/llvm/utils/profcheck-xfail.txt @@ -493,8 +493,6 @@ Transforms/LowerSwitch/do-not-handle-impossible-values.ll Transforms/LowerSwitch/feature.ll Transforms/LowerSwitch/fold-popular-case-to-unreachable-default.ll Transforms/LowerSwitch/pr59316.ll -Transforms/LowerTypeTests/import.ll -Transforms/LowerTypeTests/simple.ll Transforms/MergeFunc/2011-02-08-RemoveEqual.ll Transforms/MergeFunc/apply_function_attributes.ll Transforms/MergeFunc/call-and-invoke-with-ranges-attr.ll `````````` </details> https://github.com/llvm/llvm-project/pull/170752 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
