https://github.com/arichardson created https://github.com/llvm/llvm-project/pull/171254
Previously we would assert when a ValueTypeByHwMode was missing a case for the current mode, now we report an error instead. Interestingly this error only ocurrs when the DAG patterns use RegClassByHwMode, but not normal RegisterClass instances. Found while I added RegClassByHwMode to RISC-V and was getting an assertion due to `XLenFVT`/`XLenVecI32VT` not having an entry for the default mode. _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
