github-actions[bot] wrote:
<!--PREMERGE ADVISOR COMMENT: Windows-->
# :window: Windows x64 Test Results
* 128590 tests passed
* 2806 tests skipped
* 1 test failed
## Failed Tests
(click on a test name to see its output)
### LLVM
<details>
<summary>LLVM.TableGen/RegClassByHwModeCompressPat.td</summary>
```
Exit Code: 1
Command Output (stdout):
--
# RUN: at line 1
c:\_work\llvm-project\llvm-project\build\bin\llvm-tblgen.exe
--gen-compress-inst-emitter -I
C:\_work\llvm-project\llvm-project\llvm\test\TableGen/../../include -I
C:\_work\llvm-project\llvm-project\llvm\test\TableGen
C:\_work\llvm-project\llvm-project\llvm\test\TableGen\RegClassByHwModeCompressPat.td
-o - | c:\_work\llvm-project\llvm-project\build\bin\filecheck.exe
C:\_work\llvm-project\llvm-project\llvm\test\TableGen\RegClassByHwModeCompressPat.td
# executed command:
'c:\_work\llvm-project\llvm-project\build\bin\llvm-tblgen.exe'
--gen-compress-inst-emitter -I
'C:\_work\llvm-project\llvm-project\llvm\test\TableGen/../../include' -I
'C:\_work\llvm-project\llvm-project\llvm\test\TableGen'
'C:\_work\llvm-project\llvm-project\llvm\test\TableGen\RegClassByHwModeCompressPat.td'
-o -
# note: command had no output on stdout or stderr
# executed command:
'c:\_work\llvm-project\llvm-project\build\bin\filecheck.exe'
'C:\_work\llvm-project\llvm-project\llvm\test\TableGen\RegClassByHwModeCompressPat.td'
# .---command stderr------------
# |
C:\_work\llvm-project\llvm-project\llvm\test\TableGen\RegClassByHwModeCompressPat.td:94:16:
error: CHECK-NEXT: expected string not found in input
# | // CHECK-NEXT:
MyTargetMCRegisterClasses[STI.getInstrInfo().getOpRegClassID(MI.getDesc().operands()[1])].contains(MI.getOperand(1).getReg()))
{
# | ^
# | <stdin>:22:29: note: scanning from here
# | MI.getOperand(1).isReg() &&
# | ^
# | <stdin>:63:2: note: possible intended match here
# |
MyTargetMCRegisterClasses[MyTarget::XRegsRegClassID].contains(MI.getOperand(1).getReg()))
{
# | ^
# |
# | Input file: <stdin>
# | Check file:
C:\_work\llvm-project\llvm-project\llvm\test\TableGen\RegClassByHwModeCompressPat.td
# |
# | -dump-input=help explains the following input dump.
# |
# | Input was:
# | <<<<<<
# | .
# | .
# | .
# | 17: [[maybe_unused]] unsigned HwModeId =
STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo); switch (MI.getOpcode()) {
# | 18: default: return false;
# | 19: case MyTarget::PTR_MOV: {
# | 20: if (MI.getOperand(1).isReg() && MI.getOperand(0).isReg() &&
# | 21: (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
# | 22: MI.getOperand(1).isReg() &&
# | next:94'0 X error: no match found
# | 23:
MyTargetMCRegisterClasses[MyTargetRegClassByHwModeTables[HwModeId][MyTarget::PtrRC]].contains(MI.getOperand(1).getReg()))
{
# | next:94'0
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# | 24: // ptr_mov.tied $dst, $src
# | next:94'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# | 25: OutInst.setOpcode(MyTarget::PTR_MOV_TIED);
# | next:94'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# | 26: // Operand: dst
# | next:94'0 ~~~~~~~~~~~~~~~~~
# | 27: OutInst.addOperand(MI.getOperand(1));
# | next:94'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# | .
# | .
# | .
# | 58: return true;
# | next:94'0 ~~~~~~~~~~~~~~
# | 59: } // if
# | next:94'0 ~~~~~~~~~
# | 60: if (MI.getOperand(1).isReg() && MI.getOperand(0).isReg() &&
# | next:94'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# | 61: (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
# | next:94'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# | 62: MI.getOperand(1).isReg() &&
# | next:94'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# | 63:
MyTargetMCRegisterClasses[MyTarget::XRegsRegClassID].contains(MI.getOperand(1).getReg()))
{
# | next:94'0
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# | next:94'1 ?
possible intended match
# | 64: // x_mov.tied $dst, $src
# | next:94'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~
# | 65: OutInst.setOpcode(MyTarget::X_MOV_TIED);
# | next:94'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# | 66: // Operand: dst
# | next:94'0 ~~~~~~~~~~~~~~~~~
# | 67: OutInst.addOperand(MI.getOperand(1));
# | next:94'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# | 68: // Operand: src
# | next:94'0 ~~~~~~~~~~~~~~~~~
# | .
# | .
# | .
# | >>>>>>
# `-----------------------------
# error: command failed with exit status: 1
--
```
</details>
If these failures are unrelated to your changes (for example tests are broken
or flaky at HEAD), please open an issue at
https://github.com/llvm/llvm-project/issues and add the `infrastructure` label.
https://github.com/llvm/llvm-project/pull/171061
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