https://github.com/kasuga-fj created https://github.com/llvm/llvm-project/pull/174393
None >From 2158c88849ffc6a06e36bc745a1c6d386ed13e69 Mon Sep 17 00:00:00 2001 From: Ryotaro Kasuga <[email protected]> Date: Fri, 26 Dec 2025 10:43:32 +0000 Subject: [PATCH] [MachinePipeliner] Remove isLoopCarriedDep from computeStart --- llvm/include/llvm/CodeGen/MachinePipeliner.h | 10 ---- llvm/lib/CodeGen/MachinePipeliner.cpp | 60 ------------------- ...instruction-scheduled-at-correct-cycle.mir | 6 +- 3 files changed, 3 insertions(+), 73 deletions(-) diff --git a/llvm/include/llvm/CodeGen/MachinePipeliner.h b/llvm/include/llvm/CodeGen/MachinePipeliner.h index c90ff4f3daa47..a22ccb2d77188 100644 --- a/llvm/include/llvm/CodeGen/MachinePipeliner.h +++ b/llvm/include/llvm/CodeGen/MachinePipeliner.h @@ -779,16 +779,6 @@ class SMSchedule { /// Return the last cycle in the finalized schedule. int getFinalCycle() const { return FirstCycle + InitiationInterval - 1; } - /// Return the cycle of the earliest scheduled instruction in the dependence - /// chain. - int earliestCycleInChain(const SwingSchedulerDDGEdge &Dep, - const SwingSchedulerDDG *DDG); - - /// Return the cycle of the latest scheduled instruction in the dependence - /// chain. - int latestCycleInChain(const SwingSchedulerDDGEdge &Dep, - const SwingSchedulerDDG *DDG); - void computeStart(SUnit *SU, int *MaxEarlyStart, int *MinLateStart, int II, SwingSchedulerDAG *DAG); bool insert(SUnit *SU, int StartCycle, int EndCycle, int II); diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp index 72211611d91cc..8ef5444be266a 100644 --- a/llvm/lib/CodeGen/MachinePipeliner.cpp +++ b/llvm/lib/CodeGen/MachinePipeliner.cpp @@ -3312,54 +3312,6 @@ bool SMSchedule::insert(SUnit *SU, int StartCycle, int EndCycle, int II) { return false; } -// Return the cycle of the earliest scheduled instruction in the chain. -int SMSchedule::earliestCycleInChain(const SwingSchedulerDDGEdge &Dep, - const SwingSchedulerDDG *DDG) { - SmallPtrSet<SUnit *, 8> Visited; - SmallVector<SwingSchedulerDDGEdge, 8> Worklist; - Worklist.push_back(Dep); - int EarlyCycle = INT_MAX; - while (!Worklist.empty()) { - const SwingSchedulerDDGEdge &Cur = Worklist.pop_back_val(); - SUnit *PrevSU = Cur.getSrc(); - if (Visited.count(PrevSU)) - continue; - std::map<SUnit *, int>::const_iterator it = InstrToCycle.find(PrevSU); - if (it == InstrToCycle.end()) - continue; - EarlyCycle = std::min(EarlyCycle, it->second); - for (const auto &IE : DDG->getInEdges(PrevSU)) - if (IE.isOrderDep() || IE.isOutputDep()) - Worklist.push_back(IE); - Visited.insert(PrevSU); - } - return EarlyCycle; -} - -// Return the cycle of the latest scheduled instruction in the chain. -int SMSchedule::latestCycleInChain(const SwingSchedulerDDGEdge &Dep, - const SwingSchedulerDDG *DDG) { - SmallPtrSet<SUnit *, 8> Visited; - SmallVector<SwingSchedulerDDGEdge, 8> Worklist; - Worklist.push_back(Dep); - int LateCycle = INT_MIN; - while (!Worklist.empty()) { - const SwingSchedulerDDGEdge &Cur = Worklist.pop_back_val(); - SUnit *SuccSU = Cur.getDst(); - if (Visited.count(SuccSU) || SuccSU->isBoundaryNode()) - continue; - std::map<SUnit *, int>::const_iterator it = InstrToCycle.find(SuccSU); - if (it == InstrToCycle.end()) - continue; - LateCycle = std::max(LateCycle, it->second); - for (const auto &OE : DDG->getOutEdges(SuccSU)) - if (OE.isOrderDep() || OE.isOutputDep()) - Worklist.push_back(OE); - Visited.insert(SuccSU); - } - return LateCycle; -} - /// If an instruction has a use that spans multiple iterations, then /// return true. These instructions are characterized by having a back-ege /// to a Phi, which contains a reference to another Phi. @@ -3385,12 +3337,6 @@ void SMSchedule::computeStart(SUnit *SU, int *MaxEarlyStart, int *MinLateStart, for (SUnit *I : getInstructions(cycle)) { for (const auto &IE : DDG->getInEdges(SU)) { if (IE.getSrc() == I) { - // FIXME: Add reverse edge to `DDG` instead of calling - // `isLoopCarriedDep` - if (DAG->isLoopCarriedDep(IE)) { - int End = earliestCycleInChain(IE, DDG) + (II - 1); - *MinLateStart = std::min(*MinLateStart, End); - } int EarlyStart = cycle + IE.getLatency() - IE.getDistance() * II; *MaxEarlyStart = std::max(*MaxEarlyStart, EarlyStart); } @@ -3398,12 +3344,6 @@ void SMSchedule::computeStart(SUnit *SU, int *MaxEarlyStart, int *MinLateStart, for (const auto &OE : DDG->getOutEdges(SU)) { if (OE.getDst() == I) { - // FIXME: Add reverse edge to `DDG` instead of calling - // `isLoopCarriedDep` - if (DAG->isLoopCarriedDep(OE)) { - int Start = latestCycleInChain(OE, DDG) + 1 - II; - *MaxEarlyStart = std::max(*MaxEarlyStart, Start); - } int LateStart = cycle - OE.getLatency() + OE.getDistance() * II; *MinLateStart = std::min(*MinLateStart, LateStart); } diff --git a/llvm/test/CodeGen/AArch64/sms-instruction-scheduled-at-correct-cycle.mir b/llvm/test/CodeGen/AArch64/sms-instruction-scheduled-at-correct-cycle.mir index c1014b296cad3..81bd25b700ba8 100644 --- a/llvm/test/CodeGen/AArch64/sms-instruction-scheduled-at-correct-cycle.mir +++ b/llvm/test/CodeGen/AArch64/sms-instruction-scheduled-at-correct-cycle.mir @@ -6,9 +6,9 @@ # CHECK: {{^ *}}Try to schedule with 47 # CHECK: {{^ *}}Inst (11) %48:fpr128 = LDRQui %35:gpr64sp, 0 :: (load (s128) from %ir.lsr.iv63, align 4, !tbaa !0) # CHECK-EMPTY: -# CHECK-NEXT: {{^ *}}es: ffffffe9 ls: ffffffe9 -# CHECK-NEXT: {{^ *}}Trying to insert node between -23 and -23 II: 47 -# CHECK-NEXT: {{^ *}}failed to insert at cycle -23 %48:fpr128 = LDRQui %35:gpr64sp, 0 :: (load (s128) from %ir.lsr.iv63, align 4, !tbaa !0) +# CHECK-NEXT: {{^ *}}es: ffffffe8 ls: ffffffe9 +# CHECK-NEXT: {{^ *}}Trying to insert node between -24 and -23 II: 47 +# CHECK-NEXT: {{^ *}}insert at cycle -24 %48:fpr128 = LDRQui %35:gpr64sp, 0 :: (load (s128) from %ir.lsr.iv63, align 4, !tbaa !0) --- | target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
