Author: Sam Elliott Date: 2026-01-15T07:52:01-08:00 New Revision: a25094d4320b28adbd85a90c08047fc041b71ef5
URL: https://github.com/llvm/llvm-project/commit/a25094d4320b28adbd85a90c08047fc041b71ef5 DIFF: https://github.com/llvm/llvm-project/commit/a25094d4320b28adbd85a90c08047fc041b71ef5.diff LOG: Revert "[NFC][MI] Tidy Up RegState enum use (1/2) (#176091)" This reverts commit 1d616cdca3aba9d22f120888bb6b09b75ca90b92. Added: Modified: llvm/docs/MIRLangRef.rst llvm/include/llvm/CodeGen/MachineInstrBuilder.h llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp llvm/lib/CodeGen/MIRParser/MIParser.cpp llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.cpp llvm/lib/Target/AArch64/AArch64InstrInfo.cpp llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp llvm/lib/Target/AMDGPU/R600MachineCFGStructurizer.cpp llvm/lib/Target/AMDGPU/SIInstrInfo.cpp llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp llvm/lib/Target/ARM/Thumb2SizeReduction.cpp llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp llvm/lib/Target/PowerPC/PPCISelLowering.cpp llvm/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/lib/Target/RISCV/RISCVInstrInfo.cpp llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp llvm/lib/Target/X86/X86FixupLEAs.cpp Removed: ################################################################################ diff --git a/llvm/docs/MIRLangRef.rst b/llvm/docs/MIRLangRef.rst index efb20520db1b1..32c96d197a027 100644 --- a/llvm/docs/MIRLangRef.rst +++ b/llvm/docs/MIRLangRef.rst @@ -550,26 +550,34 @@ corresponding internal ``llvm::RegState`` representation: - Internal Value - Meaning - * - ``def`` - - ``RegState::Define`` - - Register definition. - * - ``implicit`` - ``RegState::Implicit`` - Not emitted register (e.g., carry, or temporary result). - * - ``killed`` - - ``RegState::Kill`` - - The last use of a register. + * - ``implicit-def`` + - ``RegState::ImplicitDefine`` + - ``implicit`` and ``def`` + + * - ``def`` + - ``RegState::Define`` + - Register definition. * - ``dead`` - ``RegState::Dead`` - Unused definition. + * - ``killed`` + - ``RegState::Kill`` + - The last use of a register. + * - ``undef`` - ``RegState::Undef`` - Value of the register doesn't matter. + * - ``internal`` + - ``RegState::InternalRead`` + - Register reads a value that is defined inside the same instruction or bundle. + * - ``early-clobber`` - ``RegState::EarlyClobber`` - Register definition happens before uses. @@ -578,18 +586,10 @@ corresponding internal ``llvm::RegState`` representation: - ``RegState::Debug`` - Register 'use' is for debugging purpose. - * - ``internal`` - - ``RegState::InternalRead`` - - Register reads a value that is defined inside the same instruction or bundle. - * - ``renamable`` - ``RegState::Renamable`` - Register that may be renamed. - * - ``implicit-def`` - - ``RegState::ImplicitDefine`` - - ``implicit`` and ``def`` - .. _subregister-indices: Subregister Indices diff --git a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h index 8269dc9221153..060f0c41de73a 100644 --- a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h +++ b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h @@ -43,11 +43,6 @@ namespace RegState { // Keep this in sync with the table in MIRLangRef.rst. enum { - /// No Specific Flags - NoFlags = 0x0, - // Reserved value, to detect if someone is passing `true` rather than this - // enum. - _Reserved = 0x1, /// Register definition. Define = 0x2, /// Not emitted register (e.g. carry, or temporary result). @@ -67,7 +62,6 @@ enum { InternalRead = 0x100, /// Register that may be renamed. Renamable = 0x200, - // Combinations of above flags DefineNoRead = Define | Undef, ImplicitDefine = Implicit | Define, ImplicitKill = Implicit | Kill @@ -75,52 +69,6 @@ enum { } // end namespace RegState -constexpr unsigned getDefRegState(bool B) { - return B ? RegState::Define : RegState::NoFlags; -} -constexpr unsigned getImplRegState(bool B) { - return B ? RegState::Implicit : RegState::NoFlags; -} -constexpr unsigned getKillRegState(bool B) { - return B ? RegState::Kill : RegState::NoFlags; -} -constexpr unsigned getDeadRegState(bool B) { - return B ? RegState::Dead : RegState::NoFlags; -} -constexpr unsigned getUndefRegState(bool B) { - return B ? RegState::Undef : RegState::NoFlags; -} -constexpr unsigned getEarlyClobberRegState(bool B) { - return B ? RegState::EarlyClobber : RegState::NoFlags; -} -constexpr unsigned getDebugRegState(bool B) { - return B ? RegState::Debug : RegState::NoFlags; -} -constexpr unsigned getInternalReadRegState(bool B) { - return B ? RegState::InternalRead : RegState::NoFlags; -} -constexpr unsigned getRenamableRegState(bool B) { - return B ? RegState::Renamable : RegState::NoFlags; -} - -constexpr bool hasRegState(unsigned Value, unsigned Test) { - return (Value & Test) == Test; -} - -/// Get all register state flags from machine operand \p RegOp. -constexpr unsigned getRegState(const MachineOperand &RegOp) { - assert(RegOp.isReg() && "Not a register operand"); - return getDefRegState(RegOp.isDef()) | getImplRegState(RegOp.isImplicit()) | - getKillRegState(RegOp.isKill()) | getDeadRegState(RegOp.isDead()) | - getUndefRegState(RegOp.isUndef()) | - // FIXME: why is this not included - // getEarlyClobberRegState(RegOp.isEarlyClobber()) | - getInternalReadRegState(RegOp.isInternalRead()) | - getDebugRegState(RegOp.isDebug()) | - getRenamableRegState(RegOp.getReg().isPhysical() && - RegOp.isRenamable()); -} - /// Set of metadata that should be preserved when using BuildMI(). This provides /// a more convenient way of preserving certain data from the original /// instruction. @@ -190,21 +138,21 @@ class MachineInstrBuilder { Register getReg(unsigned Idx) const { return MI->getOperand(Idx).getReg(); } /// Add a new virtual register operand. - const MachineInstrBuilder &addReg(Register RegNo, unsigned Flags = 0, + const MachineInstrBuilder &addReg(Register RegNo, unsigned flags = 0, unsigned SubReg = 0) const { - assert(!hasRegState(Flags, RegState::_Reserved) && + assert((flags & 0x1) == 0 && "Passing in 'true' to addReg is forbidden! Use enums instead."); - MI->addOperand(*MF, MachineOperand::CreateReg( - RegNo, hasRegState(Flags, RegState::Define), - hasRegState(Flags, RegState::Implicit), - hasRegState(Flags, RegState::Kill), - hasRegState(Flags, RegState::Dead), - hasRegState(Flags, RegState::Undef), - hasRegState(Flags, RegState::EarlyClobber), SubReg, - hasRegState(Flags, RegState::Debug), - hasRegState(Flags, RegState::InternalRead), - hasRegState(Flags, RegState::Renamable))); - + MI->addOperand(*MF, MachineOperand::CreateReg(RegNo, + flags & RegState::Define, + flags & RegState::Implicit, + flags & RegState::Kill, + flags & RegState::Dead, + flags & RegState::Undef, + flags & RegState::EarlyClobber, + SubReg, + flags & RegState::Debug, + flags & RegState::InternalRead, + flags & RegState::Renamable)); return *this; } @@ -218,7 +166,7 @@ class MachineInstrBuilder { /// `RegState::Define` when calling this function. const MachineInstrBuilder &addUse(Register RegNo, unsigned Flags = 0, unsigned SubReg = 0) const { - assert(!hasRegState(Flags, RegState::Define) && + assert(!(Flags & RegState::Define) && "Misleading addUse defines register, use addReg instead."); return addReg(RegNo, Flags, SubReg); } @@ -608,6 +556,43 @@ LLVM_ABI MachineInstr *buildDbgValueForSpill( LLVM_ABI void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg); +inline unsigned getDefRegState(bool B) { + return B ? RegState::Define : 0; +} +inline unsigned getImplRegState(bool B) { + return B ? RegState::Implicit : 0; +} +inline unsigned getKillRegState(bool B) { + return B ? RegState::Kill : 0; +} +inline unsigned getDeadRegState(bool B) { + return B ? RegState::Dead : 0; +} +inline unsigned getUndefRegState(bool B) { + return B ? RegState::Undef : 0; +} +inline unsigned getInternalReadRegState(bool B) { + return B ? RegState::InternalRead : 0; +} +inline unsigned getDebugRegState(bool B) { + return B ? RegState::Debug : 0; +} +inline unsigned getRenamableRegState(bool B) { + return B ? RegState::Renamable : 0; +} + +/// Get all register state flags from machine operand \p RegOp. +inline unsigned getRegState(const MachineOperand &RegOp) { + assert(RegOp.isReg() && "Not a register operand"); + return getDefRegState(RegOp.isDef()) | getImplRegState(RegOp.isImplicit()) | + getKillRegState(RegOp.isKill()) | getDeadRegState(RegOp.isDead()) | + getUndefRegState(RegOp.isUndef()) | + getInternalReadRegState(RegOp.isInternalRead()) | + getDebugRegState(RegOp.isDebug()) | + getRenamableRegState(RegOp.getReg().isPhysical() && + RegOp.isRenamable()); +} + /// Helper class for constructing bundles of MachineInstrs. /// /// MIBundleBuilder can create a bundle from scratch by inserting new diff --git a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp index f16a175af2357..2927b075fc360 100644 --- a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp +++ b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp @@ -368,9 +368,9 @@ bool InlineAsmLowering::lowerInlineAsm( Inst.addImm(Flag); for (Register Reg : OpInfo.Regs) { - Inst.addReg(Reg, RegState::Define | - getImplRegState(Reg.isPhysical()) | - getEarlyClobberRegState(OpInfo.isEarlyClobber)); + Inst.addReg(Reg, + RegState::Define | getImplRegState(Reg.isPhysical()) | + (OpInfo.isEarlyClobber ? RegState::EarlyClobber : 0)); } // Remember this output operand for later processing diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp index 1071cf00aa843..baac77fbd2dc0 100644 --- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp @@ -1768,7 +1768,7 @@ bool MIParser::assignRegisterTies(MachineInstr &MI, bool MIParser::parseRegisterOperand(MachineOperand &Dest, std::optional<unsigned> &TiedDefIdx, bool IsDef) { - unsigned Flags = getDefRegState(IsDef); + unsigned Flags = IsDef ? RegState::Define : 0; while (Token.isRegisterFlag()) { if (parseRegisterFlag(Flags)) return true; @@ -1795,7 +1795,7 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest, return true; } MachineRegisterInfo &MRI = MF.getRegInfo(); - if (!hasRegState(Flags, RegState::Define)) { + if ((Flags & RegState::Define) == 0) { if (consumeIfPresent(MIToken::lparen)) { unsigned Idx; if (!parseRegisterTiedDefIndex(Idx)) @@ -1843,23 +1843,19 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest, return error("generic virtual registers must have a type"); } - if (hasRegState(Flags, RegState::Define)) { - if (hasRegState(Flags, RegState::Kill)) + if (Flags & RegState::Define) { + if (Flags & RegState::Kill) return error("cannot have a killed def operand"); } else { - if (hasRegState(Flags, RegState::Dead)) + if (Flags & RegState::Dead) return error("cannot have a dead use operand"); } - Dest = MachineOperand::CreateReg(Reg, hasRegState(Flags, RegState::Define), - hasRegState(Flags, RegState::Implicit), - hasRegState(Flags, RegState::Kill), - hasRegState(Flags, RegState::Dead), - hasRegState(Flags, RegState::Undef), - hasRegState(Flags, RegState::EarlyClobber), - SubReg, hasRegState(Flags, RegState::Debug), - hasRegState(Flags, RegState::InternalRead), - hasRegState(Flags, RegState::Renamable)); + Dest = MachineOperand::CreateReg( + Reg, Flags & RegState::Define, Flags & RegState::Implicit, + Flags & RegState::Kill, Flags & RegState::Dead, Flags & RegState::Undef, + Flags & RegState::EarlyClobber, SubReg, Flags & RegState::Debug, + Flags & RegState::InternalRead, Flags & RegState::Renamable); return false; } diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp index 173bcebf5d3ca..473aaa94242eb 100644 --- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp +++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp @@ -137,8 +137,8 @@ bool AArch64ExpandPseudo::expandMOVImm(MachineBasicBlock &MBB, unsigned BitSize) { MachineInstr &MI = *MBBI; Register DstReg = MI.getOperand(0).getReg(); - unsigned RenamableState = - getRenamableRegState(MI.getOperand(0).isRenamable()); + uint64_t RenamableState = + MI.getOperand(0).isRenamable() ? RegState::Renamable : 0; uint64_t Imm = MI.getOperand(1).getImm(); if (DstReg == AArch64::XZR || DstReg == AArch64::WZR) { @@ -617,7 +617,7 @@ bool AArch64ExpandPseudo::expand_DestructiveOp( } // Preserve undef state until DOP's reg is defined. - unsigned DOPRegState = getUndefRegState(MI.getOperand(DOPIdx).isUndef()); + unsigned DOPRegState = MI.getOperand(DOPIdx).isUndef() ? RegState::Undef : 0; // // Create the destructive operation (if required) @@ -792,8 +792,9 @@ bool AArch64ExpandPseudo::expandSVESpillFill(MachineBasicBlock &MBB, assert((Opc == AArch64::LDR_ZXI || Opc == AArch64::STR_ZXI || Opc == AArch64::LDR_PXI || Opc == AArch64::STR_PXI) && "Unexpected opcode"); - unsigned RState = - getDefRegState(Opc == AArch64::LDR_ZXI || Opc == AArch64::LDR_PXI); + unsigned RState = (Opc == AArch64::LDR_ZXI || Opc == AArch64::LDR_PXI) + ? RegState::Define + : 0; unsigned sub0 = (Opc == AArch64::LDR_ZXI || Opc == AArch64::STR_ZXI) ? AArch64::zsub0 : AArch64::psub0; diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 273823f028e25..2e96abfce72df 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -3135,7 +3135,7 @@ MachineBasicBlock *AArch64TargetLowering::EmitZTInstr(MachineInstr &MI, MachineInstrBuilder MIB; MIB = BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Opcode)) - .addReg(MI.getOperand(0).getReg(), getDefRegState(Op0IsDef)); + .addReg(MI.getOperand(0).getReg(), Op0IsDef ? RegState::Define : 0); for (unsigned I = 1; I < MI.getNumOperands(); ++I) MIB.add(MI.getOperand(I)); diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index 6b4e4c720e7dc..f07211325393d 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -4064,7 +4064,7 @@ MachineInstr *AArch64InstrInfo::emitLdStWithAddr(MachineInstr &MemI, MRI.constrainRegClass(AM.BaseReg, &AArch64::GPR64spRegClass); auto B = BuildMI(MBB, MemI, DL, get(Opcode)) .addReg(MemI.getOperand(0).getReg(), - getDefRegState(MemI.mayLoad())) + MemI.mayLoad() ? RegState::Define : 0) .addReg(AM.BaseReg) .addReg(AM.ScaledReg) .addImm(0) @@ -4085,13 +4085,13 @@ MachineInstr *AArch64InstrInfo::emitLdStWithAddr(MachineInstr &MemI, else Opcode = scaledOffsetOpcode(Opcode, Scale); - auto B = - BuildMI(MBB, MemI, DL, get(Opcode)) - .addReg(MemI.getOperand(0).getReg(), getDefRegState(MemI.mayLoad())) - .addReg(AM.BaseReg) - .addImm(AM.Displacement / Scale) - .setMemRefs(MemI.memoperands()) - .setMIFlags(MemI.getFlags()); + auto B = BuildMI(MBB, MemI, DL, get(Opcode)) + .addReg(MemI.getOperand(0).getReg(), + MemI.mayLoad() ? RegState::Define : 0) + .addReg(AM.BaseReg) + .addImm(AM.Displacement / Scale) + .setMemRefs(MemI.memoperands()) + .setMIFlags(MemI.getFlags()); return B.getInstr(); } @@ -4110,15 +4110,15 @@ MachineInstr *AArch64InstrInfo::emitLdStWithAddr(MachineInstr &MemI, BuildMI(MBB, MemI, DL, get(TargetOpcode::COPY), OffsetReg) .addReg(AM.ScaledReg, 0, AArch64::sub_32); } - auto B = - BuildMI(MBB, MemI, DL, get(Opcode)) - .addReg(MemI.getOperand(0).getReg(), getDefRegState(MemI.mayLoad())) - .addReg(AM.BaseReg) - .addReg(OffsetReg) - .addImm(AM.Form == ExtAddrMode::Formula::SExtScaledReg) - .addImm(AM.Scale != 1) - .setMemRefs(MemI.memoperands()) - .setMIFlags(MemI.getFlags()); + auto B = BuildMI(MBB, MemI, DL, get(Opcode)) + .addReg(MemI.getOperand(0).getReg(), + MemI.mayLoad() ? RegState::Define : 0) + .addReg(AM.BaseReg) + .addReg(OffsetReg) + .addImm(AM.Form == ExtAddrMode::Formula::SExtScaledReg) + .addImm(AM.Scale != 1) + .setMemRefs(MemI.memoperands()) + .setMIFlags(MemI.getFlags()); return B.getInstr(); } diff --git a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp index 1d6f2ec3b3aa5..464cbec6c46bc 100644 --- a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp +++ b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp @@ -256,7 +256,7 @@ MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI, TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst)->getReg()), *MRI)); auto *Def = getVRegSubRegDef(CombOldVGPR, *MRI); - DPPInst.addReg(CombOldVGPR.Reg, getUndefRegState(!Def), + DPPInst.addReg(CombOldVGPR.Reg, Def ? 0 : RegState::Undef, CombOldVGPR.SubReg); ++NumOperands; } else if (TII->isVOPC(DPPOp) || (TII->isVOP3(DPPOp) && OrigOpE32 != -1 && diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp index 9838f1b1ef32a..44a4058525851 100644 --- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp +++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp @@ -1336,8 +1336,8 @@ bool GCNHazardRecognizer::fixVcmpxPermlaneHazards(MachineInstr *MI) { bool IsUndef = Src0->isUndef(); BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32)) - .addReg(Reg, RegState::Define | getDeadRegState(IsUndef)) - .addReg(Reg, IsUndef ? RegState::Undef : RegState::Kill); + .addReg(Reg, RegState::Define | (IsUndef ? RegState::Dead : 0)) + .addReg(Reg, IsUndef ? RegState::Undef : RegState::Kill); return true; } diff --git a/llvm/lib/Target/AMDGPU/R600MachineCFGStructurizer.cpp b/llvm/lib/Target/AMDGPU/R600MachineCFGStructurizer.cpp index 56d1a194b7384..0ee5f082aeeef 100644 --- a/llvm/lib/Target/AMDGPU/R600MachineCFGStructurizer.cpp +++ b/llvm/lib/Target/AMDGPU/R600MachineCFGStructurizer.cpp @@ -464,7 +464,7 @@ void R600MachineCFGStructurizer::insertCondBranchBefore( MachineInstr *NewMI = MF->CreateMachineInstr(TII->get(NewOpcode), DL); MBB->insert(I, NewMI); MachineInstrBuilder MIB(*MF, NewMI); - MIB.addReg(OldMI->getOperand(1).getReg()); + MIB.addReg(OldMI->getOperand(1).getReg(), false); SHOWNEWINSTR(NewMI); //erase later oldInstr->eraseFromParent(); } @@ -476,7 +476,7 @@ void R600MachineCFGStructurizer::insertCondBranchBefore( MachineInstr *NewInstr = MF->CreateMachineInstr(TII->get(NewOpcode), DL); //insert before blk->insert(I, NewInstr); - MachineInstrBuilder(*MF, NewInstr).addReg(RegNum); + MachineInstrBuilder(*MF, NewInstr).addReg(RegNum, false); SHOWNEWINSTR(NewInstr); } diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index be6087c76bd9a..829817c9a027d 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -2305,11 +2305,11 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { assert(VecReg == MI.getOperand(1).getReg()); MachineInstrBuilder MIB = - BuildMI(MBB, MI, DL, OpDesc) - .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) - .add(MI.getOperand(2)) - .addReg(VecReg, RegState::ImplicitDefine) - .addReg(VecReg, RegState::Implicit | getUndefRegState(IsUndef)); + BuildMI(MBB, MI, DL, OpDesc) + .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) + .add(MI.getOperand(2)) + .addReg(VecReg, RegState::ImplicitDefine) + .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0)); const int ImpDefIdx = OpDesc.getNumOperands() + OpDesc.implicit_uses().size(); @@ -2349,7 +2349,8 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) .add(MI.getOperand(2)) .addReg(VecReg, RegState::ImplicitDefine) - .addReg(VecReg, RegState::Implicit | getUndefRegState(IsUndef)); + .addReg(VecReg, + RegState::Implicit | (IsUndef ? RegState::Undef : 0)); const int ImpDefIdx = OpDesc.getNumOperands() + OpDesc.implicit_uses().size(); @@ -2392,7 +2393,7 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_indirect_read)) .addDef(Dst) .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) - .addReg(VecReg, RegState::Implicit | getUndefRegState(IsUndef)); + .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0)); MachineInstr *SetOff = BuildMI(MBB, MI, DL, get(AMDGPU::S_SET_GPR_IDX_OFF)); @@ -2670,7 +2671,7 @@ SIInstrInfo::expandMovDPP64(MachineInstr &MI) const { if (Src.isPhysical()) MovDPP.addReg(RI.getSubReg(Src, Sub)); else - MovDPP.addReg(Src, getUndefRegState(SrcOp.isUndef()), Sub); + MovDPP.addReg(Src, SrcOp.isUndef() ? RegState::Undef : 0, Sub); } } diff --git a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp index 926c52fa027b7..acc4b3f0a68b4 100644 --- a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp +++ b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp @@ -1356,7 +1356,8 @@ void SIPeepholeSDWA::legalizeScalarOperands(MachineInstr &MI, if (Op.isImm()) Copy.addImm(Op.getImm()); else if (Op.isReg()) - Copy.addReg(Op.getReg(), getKillRegState(Op.isKill()), Op.getSubReg()); + Copy.addReg(Op.getReg(), Op.isKill() ? RegState::Kill : 0, + Op.getSubReg()); Op.ChangeToRegister(VGPR, false); } } diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 409509120c32d..3657e0a4dc936 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -2653,7 +2653,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, BuildMI(*MBB, *MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), ScavengedVGPR) .addReg(MaterializedReg, - getKillRegState(MaterializedReg != FrameReg)); + MaterializedReg != FrameReg ? RegState::Kill : 0); MaterializedReg = ScavengedVGPR; } @@ -2666,7 +2666,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, AddI32.add(MI->getOperand(1)); unsigned MaterializedRegFlags = - getKillRegState(MaterializedReg != FrameReg); + MaterializedReg != FrameReg ? RegState::Kill : 0; if (isVGPRClass(getPhysRegBaseClass(MaterializedReg))) { // If we know we have a VGPR already, it's more likely the other diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp index f4f07b4c19560..d69c09fcb39db 100644 --- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -2093,7 +2093,7 @@ static void CMSEPushCalleeSaves(const TargetInstrInfo &TII, BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL)); for (unsigned Reg = ARM::R4; Reg < ARM::R8; ++Reg) { PushMIB.addReg( - Reg, getUndefRegState(Reg != JumpReg && !LiveRegs.contains(Reg))); + Reg, Reg == JumpReg || LiveRegs.contains(Reg) ? 0 : RegState::Undef); } // Thumb1 can only tPUSH low regs, so we copy the high regs to the low @@ -2108,7 +2108,7 @@ static void CMSEPushCalleeSaves(const TargetInstrInfo &TII, if (JumpReg == LoReg) continue; BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg) - .addReg(HiReg, getUndefRegState(!LiveRegs.contains(HiReg))) + .addReg(HiReg, LiveRegs.contains(HiReg) ? 0 : RegState::Undef) .add(predOps(ARMCC::AL)); --HiReg; } @@ -2126,7 +2126,7 @@ static void CMSEPushCalleeSaves(const TargetInstrInfo &TII, if (JumpReg >= ARM::R4 && JumpReg <= ARM::R7) { Register LoReg = JumpReg == ARM::R4 ? ARM::R5 : ARM::R4; BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg) - .addReg(ARM::R8, getUndefRegState(!LiveRegs.contains(ARM::R8))) + .addReg(ARM::R8, LiveRegs.contains(ARM::R8) ? 0 : RegState::Undef) .add(predOps(ARMCC::AL)); BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)) .add(predOps(ARMCC::AL)) @@ -2139,7 +2139,7 @@ static void CMSEPushCalleeSaves(const TargetInstrInfo &TII, .add(predOps(ARMCC::AL)); for (unsigned Reg = ARM::R4; Reg < ARM::R12; ++Reg) { PushMIB.addReg( - Reg, getUndefRegState(Reg != JumpReg && !LiveRegs.contains(Reg))); + Reg, Reg == JumpReg || LiveRegs.contains(Reg) ? 0 : RegState::Undef); } } } @@ -2869,8 +2869,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, // Add the source operands (D subregs). Register D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); Register D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); - MIB.addReg(D0, getKillRegState(SrcIsKill)) - .addReg(D1, getKillRegState(SrcIsKill)); + MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0) + .addReg(D1, SrcIsKill ? RegState::Kill : 0); if (SrcIsKill) // Add an implicit kill for the Q register. MIB->addRegisterKilled(SrcReg, TRI, true); @@ -3272,9 +3272,9 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opcode == ARM::LOADDUAL ? ARM::LDRD : ARM::STRD)) .addReg(TRI->getSubReg(PairReg, ARM::gsub_0), - getDefRegState(Opcode == ARM::LOADDUAL)) + Opcode == ARM::LOADDUAL ? RegState::Define : 0) .addReg(TRI->getSubReg(PairReg, ARM::gsub_1), - getDefRegState(Opcode == ARM::LOADDUAL)); + Opcode == ARM::LOADDUAL ? RegState::Define : 0); for (const MachineOperand &MO : llvm::drop_begin(MI.operands())) MIB.add(MO); MIB.add(predOps(ARMCC::AL)); diff --git a/llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp b/llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp index 0bb637edbae96..3f9ea3757a5ee 100644 --- a/llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp +++ b/llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp @@ -408,7 +408,7 @@ void ARMFixCortexA57AES1742098::insertAESFixup( // The def and the uses are still marked as Renamable if the original register // was, to avoid having to rummage through all the other uses and defs and // unset their renamable bits. - unsigned Renamable = getRenamableRegState(OperandToFixup->isRenamable()); + unsigned Renamable = OperandToFixup->isRenamable() ? RegState::Renamable : 0; BuildMI(*FixupLoc.Block, FixupLoc.InsertionPt, DebugLoc(), TII->get(ARM::VORRq)) .addReg(RegToFixup, RegState::Define | Renamable) diff --git a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp index 500c7b5ef67ca..18e41297b1734 100644 --- a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp +++ b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp @@ -477,7 +477,7 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI, .addReg(Rn) .addImm(PredImm) .addReg(PredReg) - .addReg(Rt, getDefRegState(!IsStore)); + .addReg(Rt, IsStore ? 0 : RegState::Define); // Transfer memoperands. MIB.setMemRefs(MI->memoperands()); diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp index b8c764a0d3af0..35153c7b16c0f 100644 --- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp +++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp @@ -639,7 +639,7 @@ MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp, /// predicate. unsigned Opc = getCondTfrOpcode(SrcOp, PredSense); - unsigned DstState = RegState::Define | getUndefRegState(ReadUndef); + unsigned DstState = RegState::Define | (ReadUndef ? RegState::Undef : 0); unsigned PredState = getRegState(PredOp) & ~RegState::Kill; MachineInstrBuilder MIB; @@ -889,7 +889,7 @@ void HexagonExpandCondsets::predicateAt(const MachineOperand &DefOp, // Add the new def, then the predicate register, then the rest of the // operands. MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg()); - MB.addReg(PredOp.getReg(), getUndefRegState(PredOp.isUndef()), + MB.addReg(PredOp.getReg(), PredOp.isUndef() ? RegState::Undef : 0, PredOp.getSubReg()); while (Ox < NP) { MachineOperand &MO = MI.getOperand(Ox); diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp index bb20f79fd6fd5..8de6eea10e562 100644 --- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp @@ -915,7 +915,8 @@ LoongArchInstrInfo::emitLdStWithAddr(MachineInstr &MemI, switch (MemIOp) { default: return BuildMI(MBB, MemI, DL, get(MemIOp)) - .addReg(MemI.getOperand(0).getReg(), getDefRegState(MemI.mayLoad())) + .addReg(MemI.getOperand(0).getReg(), + MemI.mayLoad() ? RegState::Define : 0) .addReg(AM.BaseReg) .addImm(AM.Displacement) .setMemRefs(MemI.memoperands()) diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 494cd32771648..ef211bf8c8982 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -14587,7 +14587,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, BuildMI(*BB, MI, DL, MI.getOpcode() == PPC::LQX_PSEUDO ? TII->get(PPC::LQ) : TII->get(PPC::STQ)) - .addReg(Val, getDefRegState(MI.getOpcode() == PPC::LQX_PSEUDO)) + .addReg(Val, MI.getOpcode() == PPC::LQX_PSEUDO ? RegState::Define : 0) .addImm(0) .addReg(Ptr); } else if (MI.getOpcode() == PPC::LWAT_PSEUDO || diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index 7a4f3d5117245..9467c15ec6f64 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -2722,7 +2722,7 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, MachineBasicBlock::iterator MII = MI; BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(), get(TargetOpcode::COPY), CRReg) - .addReg(PPC::CR0, getKillRegState(MIOpC != NewOpC)); + .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0); // Even if CR0 register were dead before, it is alive now since the // instruction we just built uses it. diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 421134fb45d7c..cf679d786ab61 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -3340,7 +3340,8 @@ MachineInstr *RISCVInstrInfo::emitLdStWithAddr(MachineInstr &MemI, "Addressing mode not supported for folding"); return BuildMI(MBB, MemI, DL, get(MemI.getOpcode())) - .addReg(MemI.getOperand(0).getReg(), getDefRegState(MemI.mayLoad())) + .addReg(MemI.getOperand(0).getReg(), + MemI.mayLoad() ? RegState::Define : 0) .addReg(AM.BaseReg) .addImm(AM.Displacement) .setMemRefs(MemI.memoperands()) diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp index bd3e282ba944f..8b4e4fbbbd1e5 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp @@ -71,7 +71,7 @@ void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB, unsigned CopyOpcode = WebAssembly::getCopyOpcodeForRegClass(RC); BuildMI(MBB, I, DL, get(CopyOpcode), DestReg) - .addReg(SrcReg, getKillRegState(KillSrc)); + .addReg(SrcReg, KillSrc ? RegState::Kill : 0); } MachineInstr *WebAssemblyInstrInfo::commuteInstructionImpl( diff --git a/llvm/lib/Target/X86/X86FixupLEAs.cpp b/llvm/lib/Target/X86/X86FixupLEAs.cpp index 07f656fc5ccfd..6a92866f31575 100644 --- a/llvm/lib/Target/X86/X86FixupLEAs.cpp +++ b/llvm/lib/Target/X86/X86FixupLEAs.cpp @@ -528,12 +528,12 @@ bool FixupLEAsImpl::optLEAALU(MachineBasicBlock::iterator &I, NewMI1 = BuildMI(MBB, InsertPos, AluI->getDebugLoc(), TII->get(NewOpcode), AluDestReg) .addReg(AluDestReg, RegState::Kill) - .addReg(BaseReg, getKillRegState(KilledBase)); + .addReg(BaseReg, KilledBase ? RegState::Kill : 0); NewMI1->addRegisterDead(X86::EFLAGS, TRI); NewMI2 = BuildMI(MBB, InsertPos, AluI->getDebugLoc(), TII->get(NewOpcode), AluDestReg) .addReg(AluDestReg, RegState::Kill) - .addReg(IndexReg, getKillRegState(KilledIndex)); + .addReg(IndexReg, KilledIndex ? RegState::Kill : 0); NewMI2->addRegisterDead(X86::EFLAGS, TRI); // Clear the old Kill flags. _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
