================ @@ -0,0 +1,45 @@ +# RUN: llvm-mc --triple=riscv64 --mattr=+experimental-y --riscv-no-aliases --show-encoding --show-inst < %s \ +# RUN: | FileCheck --check-prefixes=CHECK,CHECK-ASM,CHECK-INT %s +# RUN: llvm-mc --triple=riscv64 --mattr=+experimental-y,+cap-mode --riscv-no-aliases --show-encoding --show-inst < %s \ +# RUN: | FileCheck --check-prefixes=CHECK,CHECK-ASM,CHECK-CAP %s +# RUN: llvm-mc --filetype=obj --triple=riscv64 --mattr=+experimental-y < %s \ +# RUN: | llvm-objdump --mattr=+experimental-y -M no-aliases -d --no-print-imm-hex - \ +# RUN: | FileCheck %s +# RUN: llvm-mc --filetype=obj --triple=riscv64 --mattr=+experimental-y,+cap-mode < %s \ +# RUN: | llvm-objdump --mattr=+experimental-y,+cap-mode -M no-aliases -d --no-print-imm-hex - \ +# RUN: | FileCheck %s + +## Both capability & normal RISC-V instruction use the same encoding, and the +## same MCInst as we rely on RegClassByHwMode to select the rigt base pointer. ---------------- topperc wrote:
```suggestion ## same MCInst as we rely on RegClassByHwMode to select the right base pointer. ``` https://github.com/llvm/llvm-project/pull/177073 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
