================
@@ -5755,28 +5761,71 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr
&MI,
break;
}
case AMDGPU::V_ADD_F32_e64:
+ case AMDGPU::V_ADD_F64_e64:
+ case AMDGPU::V_ADD_F64_e64_gfx12:
case AMDGPU::V_SUB_F32_e64: {
- Register ActiveLanesVreg =
- MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
- Register DstVreg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+ bool is32BitOpc = is32bitWaveReduceOperation(Opc);
+ const TargetRegisterClass *VregRC =
+ is32BitOpc ? &AMDGPU::VGPR_32RegClass : TRI->getVGPR64Class();
----------------
arsenm wrote:
Query instruction class from instruction
https://github.com/llvm/llvm-project/pull/170812
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