Author: Jonas Paulsson Date: 2026-01-29T08:15:25Z New Revision: 19b530052723e0c95a662e5bdb554cb607db3a39
URL: https://github.com/llvm/llvm-project/commit/19b530052723e0c95a662e5bdb554cb607db3a39 DIFF: https://github.com/llvm/llvm-project/commit/19b530052723e0c95a662e5bdb554cb607db3a39.diff LOG: [SystemZ] Precommit for moving some functions around. (#177441) In preparation for #171066 (FP16 vector support). (cherry picked from commit e0a132691fe9499857d95dc1d26994f82f7f4a44) Added: Modified: llvm/lib/Target/SystemZ/SystemZISelLowering.cpp llvm/lib/Target/SystemZ/SystemZISelLowering.h Removed: ################################################################################ diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index e979c63d03dbc..87b074194c74f 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -842,6 +842,17 @@ bool SystemZTargetLowering::useSoftFloat() const { return Subtarget.hasSoftFloat(); } +MVT SystemZTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context, + CallingConv::ID CC, + EVT VT) const { + // 128-bit single-element vector types are passed like other vectors, + // not like their element type. + if (VT.isVector() && VT.getSizeInBits() == 128 && + VT.getVectorNumElements() == 1) + return MVT::v16i8; + return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT); +} + EVT SystemZTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT VT) const { if (!VT.isVector()) @@ -6561,6 +6572,33 @@ SDValue SystemZTargetLowering::lowerSCALAR_TO_VECTOR(SDValue Op, Op.getOperand(0), DAG.getConstant(0, DL, MVT::i32)); } +// Shift the lower 2 bytes of Op to the left in order to insert into the +// upper 2 bytes of the FP register. +static SDValue convertToF16(SDValue Op, SelectionDAG &DAG) { + assert(Op.getSimpleValueType() == MVT::i64 && + "Expexted to convert i64 to f16."); + SDLoc DL(Op); + SDValue Shft = DAG.getNode(ISD::SHL, DL, MVT::i64, Op, + DAG.getConstant(48, DL, MVT::i64)); + SDValue BCast = DAG.getNode(ISD::BITCAST, DL, MVT::f64, Shft); + SDValue F16Val = + DAG.getTargetExtractSubreg(SystemZ::subreg_h16, DL, MVT::f16, BCast); + return F16Val; +} + +// Extract Op into GPR and shift the 2 f16 bytes to the right. +static SDValue convertFromF16(SDValue Op, SDLoc DL, SelectionDAG &DAG) { + assert(Op.getSimpleValueType() == MVT::f16 && + "Expected to convert f16 to i64."); + SDNode *U32 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64); + SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h16, DL, MVT::f64, + SDValue(U32, 0), Op); + SDValue BCast = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64); + SDValue Shft = DAG.getNode(ISD::SRL, DL, MVT::i64, BCast, + DAG.getConstant(48, DL, MVT::i32)); + return Shft; +} + SDValue SystemZTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { // Handle insertions of floating-point values. @@ -6951,33 +6989,6 @@ SDValue SystemZTargetLowering::lower_INT_TO_FP(SDValue Op, return Op; // Legal } -// Shift the lower 2 bytes of Op to the left in order to insert into the -// upper 2 bytes of the FP register. -static SDValue convertToF16(SDValue Op, SelectionDAG &DAG) { - assert(Op.getSimpleValueType() == MVT::i64 && - "Expexted to convert i64 to f16."); - SDLoc DL(Op); - SDValue Shft = DAG.getNode(ISD::SHL, DL, MVT::i64, Op, - DAG.getConstant(48, DL, MVT::i64)); - SDValue BCast = DAG.getNode(ISD::BITCAST, DL, MVT::f64, Shft); - SDValue F16Val = - DAG.getTargetExtractSubreg(SystemZ::subreg_h16, DL, MVT::f16, BCast); - return F16Val; -} - -// Extract Op into GPR and shift the 2 f16 bytes to the right. -static SDValue convertFromF16(SDValue Op, SDLoc DL, SelectionDAG &DAG) { - assert(Op.getSimpleValueType() == MVT::f16 && - "Expected to convert f16 to i64."); - SDNode *U32 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64); - SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h16, DL, MVT::f64, - SDValue(U32, 0), Op); - SDValue BCast = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64); - SDValue Shft = DAG.getNode(ISD::SRL, DL, MVT::i64, BCast, - DAG.getConstant(48, DL, MVT::i32)); - return Shft; -} - // Lower an f16 LOAD in case of no vector support. SDValue SystemZTargetLowering::lowerLoadF16(SDValue Op, SelectionDAG &DAG) const { diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.h b/llvm/lib/Target/SystemZ/SystemZISelLowering.h index 13a1cd1614a53..c7cc26c5527e6 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.h +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.h @@ -77,14 +77,7 @@ class SystemZTargetLowering : public TargetLowering { return TargetLowering::getNumRegisters(Context, VT); } MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, - EVT VT) const override { - // 128-bit single-element vector types are passed like other vectors, - // not like their element type. - if (VT.isVector() && VT.getSizeInBits() == 128 && - VT.getVectorNumElements() == 1) - return MVT::v16i8; - return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT); - } + EVT VT) const override; bool isCheapToSpeculateCtlz(Type *) const override { return true; } bool isCheapToSpeculateCttz(Type *) const override { return true; } bool preferZeroCompareBranch() const override { return true; } _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
