Author: Simon Pilgrim Date: 2026-02-03T09:15:27Z New Revision: 0e8db607e3cbc62b210fc4869b09457337fdee9c
URL: https://github.com/llvm/llvm-project/commit/0e8db607e3cbc62b210fc4869b09457337fdee9c DIFF: https://github.com/llvm/llvm-project/commit/0e8db607e3cbc62b210fc4869b09457337fdee9c.diff LOG: [X86] Add test coverage for #179057 (#179092) Incorrect folding of fixupimm scalar intrinsics passthrough when the mask is known zero (cherry picked from commit 618d71dc98df760d0c724cff6fa69b780e8c0372) Added: Modified: llvm/test/CodeGen/X86/avx512-intrinsics.ll Removed: ################################################################################ diff --git a/llvm/test/CodeGen/X86/avx512-intrinsics.ll b/llvm/test/CodeGen/X86/avx512-intrinsics.ll index f9b5994a18d36..21bac9e7bb04d 100644 --- a/llvm/test/CodeGen/X86/avx512-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx512-intrinsics.ll @@ -5518,6 +5518,14 @@ define <4 x float>@test_int_x86_avx512_mask_fixupimm_ss(<4 x float> %x0, <4 x fl ret <4 x float> %res4 } +define <4 x float>@test_int_x86_avx512_mask_fixupimm_ss_passthrough_zero_mask(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2) { +; CHECK-LABEL: test_int_x86_avx512_mask_fixupimm_ss_passthrough_zero_mask: +; CHECK: # %bb.0: +; CHECK-NEXT: ret{{[l|q]}} + %res = call <4 x float> @llvm.x86.avx512.mask.fixupimm.ss(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i32 5, i8 -2, i32 4) + ret <4 x float> %res +} + declare <4 x float> @llvm.x86.avx512.maskz.fixupimm.ss(<4 x float>, <4 x float>, <4 x i32>, i32, i8, i32) define <4 x float>@test_int_x86_avx512_maskz_fixupimm_ss(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i8 %x4) { @@ -5555,6 +5563,16 @@ define <4 x float>@test_int_x86_avx512_maskz_fixupimm_ss(<4 x float> %x0, <4 x f ret <4 x float> %res4 } +define <4 x float>@test_int_x86_avx512_maskz_fixupimm_ss_passthrough_zero_mask(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2) { +; CHECK-LABEL: test_int_x86_avx512_maskz_fixupimm_ss_passthrough_zero_mask: +; CHECK: # %bb.0: +; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; CHECK-NEXT: vmovss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] +; CHECK-NEXT: ret{{[l|q]}} + %res = call <4 x float> @llvm.x86.avx512.maskz.fixupimm.ss(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i32 5, i8 -2, i32 4) + ret <4 x float> %res +} + declare <16 x float> @llvm.x86.avx512.mask.fixupimm.ps.512(<16 x float>, <16 x float>, <16 x i32>, i32, i16, i32) define <16 x float>@test_int_x86_avx512_mask_fixupimm_ps_512(<16 x float> %x0, <16 x float> %x1, <16 x i32> %x2, i16 %x4) { @@ -5680,6 +5698,14 @@ define <2 x double>@test_int_x86_avx512_mask_fixupimm_sd(<2 x double> %x0, <2 x ret <2 x double> %res4 } +define <2 x double>@test_int_x86_avx512_mask_fixupimm_sd_passthrough_zero_mask(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2) { +; CHECK-LABEL: test_int_x86_avx512_mask_fixupimm_sd_passthrough_zero_mask: +; CHECK: # %bb.0: +; CHECK-NEXT: ret{{[l|q]}} + %res = call <2 x double> @llvm.x86.avx512.mask.fixupimm.sd(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2, i32 5, i8 -2, i32 4) + ret <2 x double> %res +} + declare <2 x double> @llvm.x86.avx512.maskz.fixupimm.sd(<2 x double>, <2 x double>, <2 x i64>, i32, i8, i32) define <2 x double>@test_int_x86_avx512_maskz_fixupimm_sd(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2, i8 %x4) { @@ -5717,6 +5743,16 @@ define <2 x double>@test_int_x86_avx512_maskz_fixupimm_sd(<2 x double> %x0, <2 x ret <2 x double> %res4 } +define <2 x double>@test_int_x86_avx512_maskz_fixupimm_sd_passthrough_zero_mask(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2) { +; CHECK-LABEL: test_int_x86_avx512_maskz_fixupimm_sd_passthrough_zero_mask: +; CHECK: # %bb.0: +; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] +; CHECK-NEXT: ret{{[l|q]}} + %res = call <2 x double> @llvm.x86.avx512.maskz.fixupimm.sd(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2, i32 5, i8 -2, i32 4) + ret <2 x double> %res +} + declare double @llvm.fma.f64(double, double, double) #1 declare double @llvm.x86.avx512.vfmadd.f64(double, double, double, i32) #0 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
