Author: ZhaoQi Date: 2026-02-04T10:01:35Z New Revision: 319dcc140979f67858fcf4150ebc15927889a693
URL: https://github.com/llvm/llvm-project/commit/319dcc140979f67858fcf4150ebc15927889a693 DIFF: https://github.com/llvm/llvm-project/commit/319dcc140979f67858fcf4150ebc15927889a693.diff LOG: [SelectionDAG] Use promoted types when creating nodes after type legalization (#178617) When creating new nodes with illegal types after type legalization, we should try to use promoted type to avoid creating nodes with illegal types. Fixes: https://github.com/llvm/llvm-project/issues/177155 (cherry picked from commit 38e280d8a405bb442d176b8dab18da63d3fc2810) Added: llvm/test/CodeGen/LoongArch/lsx/issue177155.ll Modified: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp Removed: ################################################################################ diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index dfd074092fc78..ff5e046f0fcd5 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -3688,6 +3688,13 @@ bool TargetLowering::SimplifyDemandedVectorElts( SDLoc DL(Op); EVT SrcVT = Src.getValueType(); EVT SrcSVT = SrcVT.getScalarType(); + + // If we're after type legalization and SrcSVT is not legal, use the + // promoted type for creating constants to avoid creating nodes with + // illegal types. + if (AfterLegalizeTypes) + SrcSVT = getLegalTypeToTransformTo(*TLO.DAG.getContext(), SrcSVT); + SmallVector<SDValue> MaskElts; MaskElts.push_back(TLO.DAG.getAllOnesConstant(DL, SrcSVT)); MaskElts.append(NumSrcElts - 1, TLO.DAG.getConstant(0, DL, SrcSVT)); diff --git a/llvm/test/CodeGen/LoongArch/lsx/issue177155.ll b/llvm/test/CodeGen/LoongArch/lsx/issue177155.ll new file mode 100644 index 0000000000000..b33544da2af73 --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lsx/issue177155.ll @@ -0,0 +1,26 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s + +define i8 @test(<2 x i32> %vecinit7) { +; CHECK-LABEL: test: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vrepli.d $vr1, 1 +; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vneg.d $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 4 +; CHECK-NEXT: ret +entry: + %0 = tail call <16 x i8> @llvm.loongarch.lsx.vadd.b(<16 x i8> splat (i8 1), <16 x i8> zeroinitializer) + %shuffle = shufflevector <16 x i8> %0, <16 x i8> zeroinitializer, <2 x i32> <i32 2, i32 0> + %1 = and <2 x i8> %shuffle, splat (i8 1) + %and = zext <2 x i8> %1 to <2 x i32> + %and.i = and <2 x i32> %vecinit7, %and + %conv.i = zext <2 x i32> %and.i to <2 x i64> + %sub.i = sub <2 x i64> zeroinitializer, %conv.i + %2 = bitcast <2 x i64> %sub.i to <16 x i8> + %conv14 = extractelement <16 x i8> %2, i64 4 + ret i8 %conv14 +} + +declare <16 x i8> @llvm.loongarch.lsx.vadd.b(<16 x i8>, <16 x i8>) _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
