https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/179657
Backport 275eea298b0fc33b02044f552195f6e297aa7801 Requested by: @androm3da >From 1f8b8892f475dcafbf67f3ea324ab91b667f3b1e Mon Sep 17 00:00:00 2001 From: Abinaya Saravanan <[email protected]> Date: Wed, 4 Feb 2026 15:37:15 +0530 Subject: [PATCH] [HEXAGON] Extend/Truncate the shift amount into i32 (#179499) Fixes a Backend error (cherry picked from commit 275eea298b0fc33b02044f552195f6e297aa7801) --- .../Target/Hexagon/HexagonISelLowering.cpp | 13 ++++++++-- .../CodeGen/Hexagon/no-invalid-node-v4i16.ll | 24 +++++++++++++++++++ 2 files changed, 35 insertions(+), 2 deletions(-) create mode 100644 llvm/test/CodeGen/Hexagon/no-invalid-node-v4i16.ll diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index e98d907350c2a..9a77694305a66 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -2343,9 +2343,18 @@ HexagonTargetLowering::getVectorShiftByInt(SDValue Op, SelectionDAG &DAG) default: llvm_unreachable("Unexpected shift opcode"); } + if (SDValue Sp = getSplatValue(Op.getOperand(1), DAG)) { + const SDLoc dl(Op); + // Canonicalize shift amount to i32 as required. + SDValue Sh = Sp; + if (Sh.getValueType() != MVT::i32) + Sh = DAG.getZExtOrTrunc(Sh, dl, MVT::i32); + + assert(Sh.getValueType() == MVT::i32 && + "Hexagon vector shift-by-int must use i32 shift operand"); + return DAG.getNode(NewOpc, dl, ty(Op), Op.getOperand(0), Sh); + } - if (SDValue Sp = getSplatValue(Op.getOperand(1), DAG)) - return DAG.getNode(NewOpc, SDLoc(Op), ty(Op), Op.getOperand(0), Sp); return SDValue(); } diff --git a/llvm/test/CodeGen/Hexagon/no-invalid-node-v4i16.ll b/llvm/test/CodeGen/Hexagon/no-invalid-node-v4i16.ll new file mode 100644 index 0000000000000..6dcaebc0b83f1 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/no-invalid-node-v4i16.ll @@ -0,0 +1,24 @@ +; REQUIRES: asserts +; RUN: llc -march=hexagon -verify-machineinstrs -o - < %s 2>&1 | FileCheck %s + +; This is a crash / fatal-error regression test: +; llc used to hit: +; LLVM ERROR: invalid node: operand #1 must have type i32, but has type i16 +; during DAG combine / ISel: +; t61: v4i16 = HexagonISD::VASR t56, Constant:i16<1> +; t56: v4i16 = mulhs ... +; +; The test ensures llc does NOT emit "LLVM ERROR" and produces assembly for the function. + +; CHECK-NOT: LLVM ERROR: +; CHECK-NOT: invalid node: +; CHECK-LABEL: sq77777777: +; CHECK: r{{[0-9]+}}:{{[0-9]+}} = vasrh(r{{[0-9]+}}:{{[0-9]+}},#1) + +target triple = "hexagon-unknown-linux-musl" + +define <8 x i16> @sq77777777(<8 x i16> %0) { +entry: + %div = sdiv <8 x i16> %0, splat (i16 7) + ret <8 x i16> %div +} _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
