================
@@ -2037,13 +2037,43 @@ bool AMDGPUDAGToDAGISel::SelectGlobalSAddr(SDNode *N,
SDValue Addr,
LHS = Addr.getOperand(0);
if (!LHS->isDivergent()) {
- // add (i64 sgpr), (*_extend (i32 vgpr))
RHS = Addr.getOperand(1);
- ScaleOffset = SelectScaleOffset(N, RHS, Subtarget->hasSignedGVSOffset());
+
if (SDValue ExtRHS = matchExtFromI32orI32(
RHS, Subtarget->hasSignedGVSOffset(), CurDAG)) {
+ // add (i64 sgpr), (*_extend (scale (i32 vgpr)))
SAddr = LHS;
VOffset = ExtRHS;
+ if (NeedIOffset && !ImmOffset &&
+ CurDAG->isBaseWithConstantOffset(ExtRHS)) {
+ // add (i64 sgpr), (zero_extend (add (scale (i32 vgpr)), (i32 imm)))
+ int64_t COffset =
+ cast<ConstantSDNode>(ExtRHS.getOperand(1))->getSExtValue();
+
+ if (TII->isLegalFLATOffset(COffset, AMDGPUAS::GLOBAL_ADDRESS,
+ SIInstrFlags::FlatGlobal)) {
+ // If the MSB of the first operand of the addition is known to be
+ // zero, which is followed by zext, we are sure overflow would not
+ // happen during addition.
+ if (RHS.getOpcode() == ISD::ZERO_EXTEND &&
+ CurDAG->SignBitIsZero(ExtRHS.getOperand(0))) {
----------------
arsenm wrote:
zext nneg flag?
https://github.com/llvm/llvm-project/pull/178608
_______________________________________________
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
