================
@@ -1577,6 +1577,11 @@ RISCVTTIImpl::getIntrinsicInstrCost(const
IntrinsicCostAttributes &ICA,
case Intrinsic::abs: {
auto LT = getTypeLegalizationCost(RetTy);
if (ST->hasVInstructions() && LT.second.isVector()) {
+ // vabs.v v10, v8
+ if (ST->hasStdExtZvabd())
----------------
wangpc-pp wrote:
Yeah, `vabs.v` can support all `SEW`s. ABD operations can accept all `SEW`s in
the initial version but the RVI suggested to restrict them to 8/16 bits for
implementation complexity/pragmatism reasons.
https://github.com/llvm/llvm-project/pull/180146
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