https://github.com/lei137 updated https://github.com/llvm/llvm-project/pull/180289
>From b9e0bb1c141960e4e2c48f0928eaef0d2e16f4b8 Mon Sep 17 00:00:00 2001 From: Lei Huang <[email protected]> Date: Fri, 6 Feb 2026 15:09:43 -0500 Subject: [PATCH 1/4] consolidate printU##Imm into a template function --- .../PowerPC/MCTargetDesc/PPCInstPrinter.cpp | 87 +++---------------- .../PowerPC/MCTargetDesc/PPCInstPrinter.h | 27 ++---- llvm/lib/Target/PowerPC/PPCInstrVSX.td | 2 +- llvm/lib/Target/PowerPC/PPCOperands.td | 12 ++- 4 files changed, 32 insertions(+), 96 deletions(-) diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp index 46d6093be3c17..7bbeea39de532 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp @@ -323,35 +323,14 @@ void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo, O << "+"; } -void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned int Value = MI->getOperand(OpNo).getImm(); - assert(Value <= 1 && "Invalid u1imm argument!"); - O << (unsigned int)Value; -} - -void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned int Value = MI->getOperand(OpNo).getImm(); - assert(Value <= 3 && "Invalid u2imm argument!"); - O << (unsigned int)Value; -} - -void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned int Value = MI->getOperand(OpNo).getImm(); - assert(Value <= 8 && "Invalid u3imm argument!"); - O << (unsigned int)Value; -} - -void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { +// Template for unsigned immediate operands with validation. +// Validates that the value fits within the specified width and prints it. +template<unsigned Width> +void PPCInstPrinter::printUImmOperand(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O) { unsigned int Value = MI->getOperand(OpNo).getImm(); - assert(Value <= 15 && "Invalid u4imm argument!"); + assert(Value <= ((1U << Width) - 1) && "Invalid uimm argument!"); O << (unsigned int)Value; } @@ -371,56 +350,16 @@ void PPCInstPrinter::printImmZeroOperand(const MCInst *MI, unsigned OpNo, O << (unsigned int)Value; } -void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned int Value = MI->getOperand(OpNo).getImm(); - assert(Value <= 31 && "Invalid u5imm argument!"); - O << (unsigned int)Value; -} - -void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned int Value = MI->getOperand(OpNo).getImm(); - assert(Value <= 63 && "Invalid u6imm argument!"); - O << (unsigned int)Value; -} - -void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned int Value = MI->getOperand(OpNo).getImm(); - assert(Value <= 127 && "Invalid u7imm argument!"); - O << (unsigned int)Value; -} - -// Operands of BUILD_VECTOR are signed and we use this to print operands -// of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and -// print as unsigned. -void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { +// Truncating version specifically for BUILD_VECTOR operands that may be +// sign-extended (e.g., -1 becomes 0xFFFFFFFF). Truncates to 8 bits without +// validation, unlike the standard printUImmOperand<8> which validates. +void PPCInstPrinter::printU8ImmOperandTrunc(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O) { unsigned char Value = MI->getOperand(OpNo).getImm(); O << (unsigned int)Value; } -void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned short Value = MI->getOperand(OpNo).getImm(); - assert(Value <= 1023 && "Invalid u10imm argument!"); - O << (unsigned short)Value; -} - -void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned short Value = MI->getOperand(OpNo).getImm(); - assert(Value <= 4095 && "Invalid u12imm argument!"); - O << (unsigned short)Value; -} - void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h index 2fbd06c5a96cf..297bfb4b8a65f 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h @@ -56,28 +56,15 @@ class PPCInstPrinter : public MCInstPrinter { void printATBitsAsHint(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - void printU1ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printU2ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printU3ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printU4ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); + // Template for unsigned immediate operands with validation + template<unsigned Width> + void printUImmOperand(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, raw_ostream &O); + void printS5ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - void printU5ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printU6ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printU7ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printU8ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printU10ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printU12ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); + void printU8ImmOperandTrunc(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, raw_ostream &O); void printS16ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printS32ImmOperand(const MCInst *MI, unsigned OpNo, diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td index 81ab59657c71e..1f6bccaf127b8 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -1707,7 +1707,7 @@ let Predicates = [HasVSX, HasP9Vector] in { RegConstraint<"$XTi = $XT">; // Vector Splat Immediate Byte - def XXSPLTIB : X_RD6_IMM8<60, 360, (outs vsrc:$XT), (ins u8imm:$IMM8), + def XXSPLTIB : X_RD6_IMM8<60, 360, (outs vsrc:$XT), (ins u8imm_trunc:$IMM8), "xxspltib $XT, $IMM8", IIC_VecPerm, []>; // When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in diff --git a/llvm/lib/Target/PowerPC/PPCOperands.td b/llvm/lib/Target/PowerPC/PPCOperands.td index 824397c6d03d7..afa255cde3ccd 100644 --- a/llvm/lib/Target/PowerPC/PPCOperands.td +++ b/llvm/lib/Target/PowerPC/PPCOperands.td @@ -26,7 +26,9 @@ class ImmediateAsmOperand<string predicate, string render="addImmOperands"> // Base class for immediate operands with optional encoder. class ImmediateOp<ValueType vt, string asmop, int width, bit is_signed = 0, string encoder = "", string decoder = ""> : Operand<vt> { - let PrintMethod = "print"#asmop#"Operand"; + let PrintMethod = !if(is_signed, + "print"#asmop#"Operand", + "printUImmOperand<"#width#">"); let ParserMatchClass = !cast<AsmOperandClass>(asmop); let OperandType = "OPERAND_IMMEDIATE"; @@ -136,6 +138,14 @@ defm u7imm : UnsignedImmediate<i32, defm u8imm : UnsignedImmediate<i32, [{ return isUInt<8>(Imm); }], NOOP_SDNodeXForm, "U8Imm", 8>; + +// Truncating version for BUILD_VECTOR operands that may be sign-extended. +// Uses the same parser class as u8imm but with a truncating print method. +def u8imm_trunc : Operand<i32> { + let PrintMethod = "printU8ImmOperandTrunc"; + let ParserMatchClass = U8Imm; + let OperandType = "OPERAND_IMMEDIATE"; +} defm u10imm : UnsignedImmediate<i32, [{ return isUInt<10>(Imm); }], NOOP_SDNodeXForm, "U10Imm", 10>; >From 04fe65c62458d380201cc5d36ee6641852a63f4b Mon Sep 17 00:00:00 2001 From: Lei Huang <[email protected]> Date: Fri, 6 Feb 2026 16:28:36 -0500 Subject: [PATCH 2/4] separate actual imm with imm with relocation --- .../PowerPC/MCTargetDesc/PPCInstPrinter.cpp | 11 +- .../PowerPC/MCTargetDesc/PPCInstPrinter.h | 7 +- llvm/lib/Target/PowerPC/PPCOperands.td | 110 ++++++++++-------- 3 files changed, 75 insertions(+), 53 deletions(-) diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp index 7bbeea39de532..48605b57ffacf 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp @@ -334,11 +334,14 @@ void PPCInstPrinter::printUImmOperand(const MCInst *MI, unsigned OpNo, O << (unsigned int)Value; } -void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { +// Template for signed immediate operands with sign extension. +// Sign-extends the value to the specified width and prints it. +template<unsigned Width> +void PPCInstPrinter::printSImmOperand(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O) { int Value = MI->getOperand(OpNo).getImm(); - Value = SignExtend32<5>(Value); + Value = SignExtend32<Width>(Value); O << (int)Value; } diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h index 297bfb4b8a65f..51a8809f070fd 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h @@ -61,8 +61,11 @@ class PPCInstPrinter : public MCInstPrinter { void printUImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - void printS5ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); + // Template for signed immediate operands with sign extension + template<unsigned Width> + void printSImmOperand(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, raw_ostream &O); + void printU8ImmOperandTrunc(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printS16ImmOperand(const MCInst *MI, unsigned OpNo, diff --git a/llvm/lib/Target/PowerPC/PPCOperands.td b/llvm/lib/Target/PowerPC/PPCOperands.td index afa255cde3ccd..f7374ad801e8f 100644 --- a/llvm/lib/Target/PowerPC/PPCOperands.td +++ b/llvm/lib/Target/PowerPC/PPCOperands.td @@ -17,73 +17,89 @@ // Base class for immediate AsmOperandClass definitions. class ImmediateAsmOperand<string predicate, string render="addImmOperands"> -: AsmOperandClass { + : AsmOperandClass { let Name = NAME; let PredicateMethod = predicate; let RenderMethod = render; } -// Base class for immediate operands with optional encoder. -class ImmediateOp<ValueType vt, string asmop, int width, bit is_signed = 0, - string encoder = "", string decoder = ""> : Operand<vt> { - let PrintMethod = !if(is_signed, - "print"#asmop#"Operand", - "printUImmOperand<"#width#">"); +// Base class for signed immediate operands. +class ImmediateOp<ValueType vt, string asmop, int width> : Operand<vt> { + let PrintMethod = "printSImmOperand<"#width#">"; + let DecoderMethod = "decodeSImmOperand<"#width#">"; let ParserMatchClass = !cast<AsmOperandClass>(asmop); let OperandType = "OPERAND_IMMEDIATE"; +} + +// Base class for unsigned immediate operands. +class UImmediateOp<ValueType vt, string asmop, int width> + : ImmediateOp<vt, asmop, width> { + let PrintMethod = "printUImmOperand<"#width#">"; + let DecoderMethod = "decodeUImmOperand<"#width#">"; +} - // Set decoder method based on signedness if not explicitly provided +// Base class for signed immediate operands with relocation. +class ImmediateRelocOp<ValueType vt, string asmop, int width, string fixup, + string decoder = ""> : Operand<vt> { + let PrintMethod = "print"#asmop#"Operand"; let DecoderMethod = !if(!eq(decoder, ""), - !if(is_signed, - "decodeSImmOperand<"#width#">", - "decodeUImmOperand<"#width#">"), + "decodeSImmOperand<"#width#">", decoder); - - // Set encoder method if provided - let EncoderMethod = !if(!eq(encoder, ""), - "", - "getImmEncoding<" # encoder # ">"); + let ParserMatchClass = !cast<AsmOperandClass>(asmop); + let EncoderMethod = "getImmEncoding<" # fixup # ">"; + let OperandType = "OPERAND_IMMEDIATE"; } +// Base class for unsigned immediate operands with relocation. +class UImmediateRelocOp<ValueType vt, string asmop, int width, string fixup, + string decoder = ""> + : ImmediateRelocOp<vt, asmop, width, fixup> { + let DecoderMethod = !if(!eq(decoder, ""), + "decodeUImmOperand<"#width#">", + decoder); +} //===----------------------------------------------------------------------===// // Multiclasses for complete immediate definitions // (AsmOperand + Operand + ImmLeaf). //===----------------------------------------------------------------------===// -// Helper multiclass that generates operand + patterns together while keeping -// them as separate definitions for GlobalISel compatibility. -multiclass ImmOpWithPatterns<ValueType vt, string asmop, int width, - bit is_signed, code pred, SDNodeXForm xform, - string encoder = ""> { - // Operand definition (for instruction operands) - def "" : ImmediateOp<vt, asmop, width, is_signed, encoder>; - - // ImmLeaf for imm nodes (for DAG pattern matching) +multiclass SignedImmediate<ValueType vt, code pred, SDNodeXForm xform, + string asmop, int width > { + def "" : ImmediateOp<vt, asmop, width>; def _pat : ImmLeaf<vt, pred, xform>; - - // TImmLeaf for timm nodes (for target-specific pattern matching, e.g., intrinsics) def _timm : TImmLeaf<vt, pred, xform>; } -// Creates Operand and separate ImmLeaf definitions for unsigned immediates. multiclass UnsignedImmediate<ValueType vt, code pred, SDNodeXForm xform, - string asmop, int width, string encoder = ""> - : ImmOpWithPatterns<vt, asmop, width, 0, pred, xform, encoder>; + string asmop, int width > { + def "" : UImmediateOp<vt, asmop, width>; + def _pat : ImmLeaf<vt, pred, xform>; + def _timm : TImmLeaf<vt, pred, xform>; +} -// Creates Operand and separate ImmLeaf definitions for signed immediates. -multiclass SignedImmediate<ValueType vt, code pred, SDNodeXForm xform, - string asmop, int width, string encoder = ""> - : ImmOpWithPatterns<vt, asmop, width, 1, pred, xform, encoder>; +multiclass SignedImmediateReloc<ValueType vt, code pred, SDNodeXForm xform, + string asmop, int width, string fixup> { + def "" : ImmediateRelocOp<vt, asmop, width, fixup>; + def _pat : ImmLeaf<vt, pred, xform>; + def _timm : TImmLeaf<vt, pred, xform>; +} + +// Helper multiclass for unsigned immediates with relocation fixup string. +multiclass UnsignedImmediateReloc<ValueType vt, code pred, SDNodeXForm xform, + string asmop, int width, string fixup> { + def "" : UImmediateRelocOp<vt, asmop, width, fixup>; + def _pat : ImmLeaf<vt, pred, xform>; + def _timm : TImmLeaf<vt, pred, xform>; +} // Multiclass for signed immediate operands with both regular and // PC-relative versions. -multiclass SignedImmediateWithPCRel<ValueType vt, code pred, - SDNodeXForm xform, string asmop, - int width, string fixup_imm, +multiclass SignedImmediateWithPCRel<ValueType vt, code pred, SDNodeXForm xform, + string asmop, int width, string fixup_imm, string fixup_pcrel> - : SignedImmediate<vt, pred, xform, asmop, width, fixup_imm> { - // PC-relative immediate: instantiate SignedImmediate with PC-relative fixup - defm _pcrel : SignedImmediate<vt, pred, xform, asmop, width, fixup_pcrel>; + : SignedImmediateReloc<vt, pred, xform, asmop, width, fixup_imm> { + // PC-relative immediate: instantiate with PC-relative fixup + defm _pcrel : SignedImmediateReloc<vt, pred, xform, asmop, width, fixup_pcrel>; } //===----------------------------------------------------------------------===// @@ -157,7 +173,7 @@ defm s5imm : SignedImmediate<i32, [{ return isInt<5>(Imm); }], NOOP_SDNodeXForm, "S5Imm", 5>; -defm s34imm : SignedImmediate<i32, +defm s34imm : SignedImmediateReloc<i32, [{ return isInt<34>(Imm); }], NOOP_SDNodeXForm, "S34Imm", 34, "PPC::fixup_ppc_imm34">; @@ -198,28 +214,28 @@ def atimm : Operand<i32> { } // Special cases: s16imm and u16imm have custom encoder methods. -defm s16imm : SignedImmediate<i32, +defm s16imm : SignedImmediateReloc<i32, [{ return isInt<16>(Imm); }], NOOP_SDNodeXForm, "S16Imm", 16, "PPC::fixup_ppc_half16">; -defm u16imm : UnsignedImmediate<i32, +defm u16imm : UnsignedImmediateReloc<i32, [{ return isUInt<16>(Imm); }], NOOP_SDNodeXForm, "U16Imm", 16, "PPC::fixup_ppc_half16">; // s16imm64 uses imm64SExt16 pattern to match the operand type. -def s16imm64 : ImmediateOp<i64, "S16Imm", 16, 1, "PPC::fixup_ppc_half16">; +def s16imm64 : ImmediateRelocOp<i64, "S16Imm", 16, "PPC::fixup_ppc_half16">; // u16imm64 uses two different patterns depending on the instruction context: // * immZExt16 - For low 16-bit immediates // * imm16ShiftedZExt - For high 16-bit immediates (shifted) -def u16imm64 : ImmediateOp<i64, "U16Imm", 16, 0, "PPC::fixup_ppc_half16">; +def u16imm64 : UImmediateRelocOp<i64, "U16Imm", 16, "PPC::fixup_ppc_half16">; // Special case: s17imm uses S16Imm print method but accepts wider range. // This operand type is used for addis/lis to allow the assembler parser // to accept immediates in the range -65536..65535 for compatibility // with the GNU assembler. The operand is treated as 16-bit otherwise. -def s17imm : ImmediateOp<i32, "S17Imm", 16, 1, "PPC::fixup_ppc_half16"> { +def s17imm : ImmediateRelocOp<i32, "S17Imm", 16, "PPC::fixup_ppc_half16"> { let PrintMethod = "printS16ImmOperand"; } -def s17imm64 : ImmediateOp<i64, "S17Imm", 16, 1, "PPC::fixup_ppc_half16"> { +def s17imm64 : ImmediateRelocOp<i64, "S17Imm", 16, "PPC::fixup_ppc_half16"> { let PrintMethod = "printS16ImmOperand"; } >From b31f068e59f91b1eb442a12168a1fb9d1c7ed3a1 Mon Sep 17 00:00:00 2001 From: Lei Huang <[email protected]> Date: Fri, 6 Feb 2026 17:25:34 -0500 Subject: [PATCH 3/4] simplify multiclass with patterns --- llvm/lib/Target/PowerPC/PPCOperands.td | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCOperands.td b/llvm/lib/Target/PowerPC/PPCOperands.td index f7374ad801e8f..c6f6886ea11f4 100644 --- a/llvm/lib/Target/PowerPC/PPCOperands.td +++ b/llvm/lib/Target/PowerPC/PPCOperands.td @@ -63,33 +63,34 @@ class UImmediateRelocOp<ValueType vt, string asmop, int width, string fixup, // (AsmOperand + Operand + ImmLeaf). //===----------------------------------------------------------------------===// -multiclass SignedImmediate<ValueType vt, code pred, SDNodeXForm xform, - string asmop, int width > { - def "" : ImmediateOp<vt, asmop, width>; +multiclass ImmPatterns<ValueType vt, code pred, SDNodeXForm xform> { def _pat : ImmLeaf<vt, pred, xform>; def _timm : TImmLeaf<vt, pred, xform>; } +multiclass SignedImmediate<ValueType vt, code pred, SDNodeXForm xform, + string asmop, int width > + : ImmPatterns<vt, pred, xform> { + def "" : ImmediateOp<vt, asmop, width>; +} + multiclass UnsignedImmediate<ValueType vt, code pred, SDNodeXForm xform, - string asmop, int width > { + string asmop, int width > + : ImmPatterns<vt, pred, xform> { def "" : UImmediateOp<vt, asmop, width>; - def _pat : ImmLeaf<vt, pred, xform>; - def _timm : TImmLeaf<vt, pred, xform>; } multiclass SignedImmediateReloc<ValueType vt, code pred, SDNodeXForm xform, - string asmop, int width, string fixup> { + string asmop, int width, string fixup> + : ImmPatterns<vt, pred, xform> { def "" : ImmediateRelocOp<vt, asmop, width, fixup>; - def _pat : ImmLeaf<vt, pred, xform>; - def _timm : TImmLeaf<vt, pred, xform>; } // Helper multiclass for unsigned immediates with relocation fixup string. multiclass UnsignedImmediateReloc<ValueType vt, code pred, SDNodeXForm xform, - string asmop, int width, string fixup> { + string asmop, int width, string fixup> + : ImmPatterns<vt, pred, xform> { def "" : UImmediateRelocOp<vt, asmop, width, fixup>; - def _pat : ImmLeaf<vt, pred, xform>; - def _timm : TImmLeaf<vt, pred, xform>; } // Multiclass for signed immediate operands with both regular and >From d3cbbe0bb7c21c7968e56b9a8ecfb1703ba0948e Mon Sep 17 00:00:00 2001 From: Lei Huang <[email protected]> Date: Mon, 9 Feb 2026 14:18:37 +0000 Subject: [PATCH 4/4] update doc --- llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h index 51a8809f070fd..ace78db324897 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h @@ -56,12 +56,12 @@ class PPCInstPrinter : public MCInstPrinter { void printATBitsAsHint(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - // Template for unsigned immediate operands with validation + // Template for unsigned immediate operands with validation. template<unsigned Width> void printUImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - // Template for signed immediate operands with sign extension + // Template for signed immediate operands with sign extension. template<unsigned Width> void printSImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
