llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-spir-v Author: Juan Manuel Martinez Caamaño (jmmartinez) <details> <summary>Changes</summary> Second part of https://github.com/llvm/llvm-project/pull/179947 where we use `SPIRVTypeInst` as much as we can. --- Patch is 278.96 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/180721.diff 15 Files Affected: - (modified) llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp (+94-94) - (modified) llvm/lib/Target/SPIRV/SPIRVBuiltins.h (+4-4) - (modified) llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp (+17-17) - (modified) llvm/lib/Target/SPIRV/SPIRVCombinerHelper.cpp (+7-7) - (modified) llvm/lib/Target/SPIRV/SPIRVCombinerHelper.h (+7-6) - (modified) llvm/lib/Target/SPIRV/SPIRVEmitNonSemanticDI.cpp (+2-2) - (modified) llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp (+201-191) - (modified) llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h (+205-166) - (modified) llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp (+37-31) - (modified) llvm/lib/Target/SPIRV/SPIRVISelLowering.h (+1-1) - (modified) llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp (+310-308) - (modified) llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp (+14-14) - (modified) llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp (+20-19) - (modified) llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp (+56-55) - (modified) llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp (+23-21) ``````````diff diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp index 4086d3228ff67..712549510e145 100644 --- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp @@ -45,11 +45,11 @@ struct IncomingCall { const DemangledBuiltin *Builtin; const Register ReturnRegister; - const SPIRVType *ReturnType; + const SPIRVTypeInst ReturnType; const SmallVectorImpl<Register> &Arguments; IncomingCall(const std::string BuiltinName, const DemangledBuiltin *Builtin, - const Register ReturnRegister, const SPIRVType *ReturnType, + const Register ReturnRegister, SPIRVTypeInst ReturnType, const SmallVectorImpl<Register> &Arguments) : BuiltinName(std::move(BuiltinName)), Builtin(Builtin), ReturnRegister(ReturnRegister), ReturnType(ReturnType), @@ -273,7 +273,7 @@ std::string lookupBuiltinNameHelper(StringRef DemangledCall, static std::unique_ptr<const SPIRV::IncomingCall> lookupBuiltin(StringRef DemangledCall, SPIRV::InstructionSet::InstructionSet Set, - Register ReturnRegister, const SPIRVType *ReturnType, + Register ReturnRegister, SPIRVTypeInst ReturnType, const SmallVectorImpl<Register> &Arguments) { std::string BuiltinName = SPIRV::lookupBuiltinNameHelper(DemangledCall); @@ -439,11 +439,11 @@ static const Type *getBlockStructType(Register ParamReg, /// depending on the expected \p ResultType. /// /// \returns Tuple of the resulting register and its type. -static std::tuple<Register, SPIRVType *> -buildBoolRegister(MachineIRBuilder &MIRBuilder, const SPIRVType *ResultType, +static std::tuple<Register, SPIRVTypeInst> +buildBoolRegister(MachineIRBuilder &MIRBuilder, SPIRVTypeInst ResultType, SPIRVGlobalRegistry *GR) { LLT Type; - SPIRVType *BoolType = GR->getOrCreateSPIRVBoolType(MIRBuilder, true); + SPIRVTypeInst BoolType = GR->getOrCreateSPIRVBoolType(MIRBuilder, true); if (ResultType->getOpcode() == SPIRV::OpTypeVector) { unsigned VectorElements = ResultType->getOperand(2).getImm(); @@ -467,8 +467,7 @@ buildBoolRegister(MachineIRBuilder &MIRBuilder, const SPIRVType *ResultType, /// depending on the expected \p ResultType. static bool buildSelectInst(MachineIRBuilder &MIRBuilder, Register ReturnRegister, Register SourceRegister, - const SPIRVType *ReturnType, - SPIRVGlobalRegistry *GR) { + SPIRVTypeInst ReturnType, SPIRVGlobalRegistry *GR) { Register TrueConst, FalseConst; if (ReturnType->getOpcode() == SPIRV::OpTypeVector) { @@ -488,7 +487,7 @@ static bool buildSelectInst(MachineIRBuilder &MIRBuilder, /// Helper function for building a load instruction loading into the /// \p DestinationReg. -static Register buildLoadInst(SPIRVType *BaseType, Register PtrRegister, +static Register buildLoadInst(SPIRVTypeInst BaseType, Register PtrRegister, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR, LLT LowLevelType, Register DestinationReg = Register(0)) { @@ -504,7 +503,7 @@ static Register buildLoadInst(SPIRVType *BaseType, Register PtrRegister, /// Helper function for building a load instruction for loading a builtin global /// variable of \p BuiltinValue value. static Register buildBuiltinVariableLoad( - MachineIRBuilder &MIRBuilder, SPIRVType *VariableType, + MachineIRBuilder &MIRBuilder, SPIRVTypeInst VariableType, SPIRVGlobalRegistry *GR, SPIRV::BuiltIn::BuiltIn BuiltinValue, LLT LLType, Register Reg = Register(0), bool isConst = true, const std::optional<SPIRV::LinkageType::LinkageType> &LinkageTy = { @@ -515,7 +514,7 @@ static Register buildBuiltinVariableLoad( NewRegister, LLT::pointer(storageClassToAddressSpace(SPIRV::StorageClass::Function), GR->getPointerSize())); - SPIRVType *PtrType = GR->getOrCreateSPIRVPointerType( + SPIRVTypeInst PtrType = GR->getOrCreateSPIRVPointerType( VariableType, MIRBuilder, SPIRV::StorageClass::Input); GR->assignSPIRVTypeToVReg(PtrType, NewRegister, MIRBuilder.getMF()); @@ -534,7 +533,7 @@ static Register buildBuiltinVariableLoad( /// Helper external function for assigning SPIRVType to a register, ensuring the /// register class and type are set in MRI. Defined in SPIRVPreLegalizer.cpp. -extern void updateRegType(Register Reg, Type *Ty, SPIRVType *SpirvTy, +extern void updateRegType(Register Reg, Type *Ty, SPIRVTypeInst SpirvTy, SPIRVGlobalRegistry *GR, MachineIRBuilder &MIB, MachineRegisterInfo &MRI); @@ -602,7 +601,7 @@ static void setRegClassIfNull(Register Reg, MachineRegisterInfo *MRI, SPIRVGlobalRegistry *GR) { if (MRI->getRegClassOrNull(Reg)) return; - SPIRVType *SpvType = GR->getSPIRVTypeForVReg(Reg); + SPIRVTypeInst SpvType = GR->getSPIRVTypeForVReg(Reg); MRI->setRegClass(Reg, SpvType ? GR->getRegClass(SpvType) : &SPIRV::iIDRegClass); } @@ -728,7 +727,7 @@ static bool buildAtomicCompareExchangeInst( Register ObjectPtr = Call->Arguments[0]; // Pointer (volatile A *object.) Register ExpectedArg = Call->Arguments[1]; // Comparator (C* expected). Register Desired = Call->Arguments[2]; // Value (C Desired). - SPIRVType *SpvDesiredTy = GR->getSPIRVTypeForVReg(Desired); + SPIRVTypeInst SpvDesiredTy = GR->getSPIRVTypeForVReg(Desired); LLT DesiredLLT = MRI->getType(Desired); assert(GR->getSPIRVTypeForVReg(ObjectPtr)->getOpcode() == @@ -739,7 +738,7 @@ static bool buildAtomicCompareExchangeInst( : ExpectedType == SPIRV::OpTypePointer); assert(GR->isScalarOfType(Desired, SPIRV::OpTypeInt)); - SPIRVType *SpvObjectPtrTy = GR->getSPIRVTypeForVReg(ObjectPtr); + SPIRVTypeInst SpvObjectPtrTy = GR->getSPIRVTypeForVReg(ObjectPtr); assert(SpvObjectPtrTy->getOperand(2).isReg() && "SPIRV type is expected"); auto StorageClass = static_cast<SPIRV::StorageClass::StorageClass>( SpvObjectPtrTy->getOperand(1).getImm()); @@ -1162,7 +1161,7 @@ static unsigned getNumComponentsForDim(SPIRV::Dim::Dim dim) { } /// Helper function for obtaining the number of size components. -static unsigned getNumSizeComponents(SPIRVType *imgType) { +static unsigned getNumSizeComponents(SPIRVTypeInst imgType) { assert(imgType->getOpcode() == SPIRV::OpTypeImage); auto dim = static_cast<SPIRV::Dim::Dim>(imgType->getOperand(2).getImm()); unsigned numComps = getNumComponentsForDim(dim); @@ -1213,7 +1212,7 @@ getBuiltinCallArguments(const SPIRV::IncomingCall *Call, uint32_t BuiltinNumber, SmallVector<Register> Arguments; for (Register Argument : Call->Arguments) { Register VecArg = Argument; - SPIRVType *ArgumentType = GR->getSPIRVTypeForVReg(Argument); + SPIRVTypeInst ArgumentType = GR->getSPIRVTypeForVReg(Argument); if (ArgumentType != Call->ReturnType) { VecArg = createVirtualRegister(Call->ReturnType, GR, MIRBuilder); auto VecSplat = MIRBuilder.buildInstr(SPIRV::OpCompositeConstruct) @@ -1291,7 +1290,7 @@ static bool generateRelationalInst(const SPIRV::IncomingCall *Call, SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode; Register CompareRegister; - SPIRVType *RelationType; + SPIRVTypeInst RelationType = nullptr; std::tie(CompareRegister, RelationType) = buildBoolRegister(MIRBuilder, Call->ReturnType, GR); @@ -1347,9 +1346,9 @@ static bool generateGroupInst(const SPIRV::IncomingCall *Call, Register Arg0; if (GroupBuiltin->HasBoolArg) { - SPIRVType *BoolType = GR->getOrCreateSPIRVBoolType(MIRBuilder, true); + SPIRVTypeInst BoolType = GR->getOrCreateSPIRVBoolType(MIRBuilder, true); Register BoolReg = Call->Arguments[0]; - SPIRVType *BoolRegType = GR->getSPIRVTypeForVReg(BoolReg); + SPIRVTypeInst BoolRegType = GR->getSPIRVTypeForVReg(BoolReg); if (!BoolRegType) report_fatal_error("Can't find a register's type definition"); MachineInstr *ArgInstruction = getDefInstrMaybeConstant(BoolReg, MRI); @@ -1375,7 +1374,7 @@ static bool generateGroupInst(const SPIRV::IncomingCall *Call, } Register GroupResultRegister = Call->ReturnRegister; - SPIRVType *GroupResultType = Call->ReturnType; + SPIRVTypeInst GroupResultType = Call->ReturnType; // TODO: maybe we need to check whether the result type is already boolean // and in this case do not insert select instruction. @@ -1401,14 +1400,14 @@ static bool generateGroupInst(const SPIRV::IncomingCall *Call, // it's a work_group_broadcast(val, local_id_x, local_id_y) or // work_group_broadcast(val, local_id_x, local_id_y, local_id_z) call. Register ElemReg = Call->Arguments[1]; - SPIRVType *ElemType = GR->getSPIRVTypeForVReg(ElemReg); + SPIRVTypeInst ElemType = GR->getSPIRVTypeForVReg(ElemReg); if (!ElemType || ElemType->getOpcode() != SPIRV::OpTypeInt) report_fatal_error("Expect an integer <LocalId> argument"); unsigned VecLen = Call->Arguments.size() - 1; VecReg = MRI->createGenericVirtualRegister( LLT::fixed_vector(VecLen, MRI->getType(ElemReg))); MRI->setRegClass(VecReg, &SPIRV::vIDRegClass); - SPIRVType *VecType = + SPIRVTypeInst VecType = GR->getOrCreateSPIRVVectorType(ElemType, VecLen, MIRBuilder, true); GR->assignSPIRVTypeToVReg(VecType, VecReg, MIRBuilder.getMF()); auto MIB = @@ -1481,7 +1480,7 @@ static bool generateIntelSubgroupsInst(const SPIRV::IncomingCall *Call, if (IntelSubgroups->IsBlock) { // Minimal number or arguments set in TableGen records is 1 - if (SPIRVType *Arg0Type = GR->getSPIRVTypeForVReg(Call->Arguments[0])) { + if (SPIRVTypeInst Arg0Type = GR->getSPIRVTypeForVReg(Call->Arguments[0])) { if (Arg0Type->getOpcode() == SPIRV::OpTypeImage) { // TODO: add required validation from the specification: // "'Image' must be an object whose type is OpTypeImage with a 'Sampled' @@ -1636,7 +1635,7 @@ static bool genWorkgroupQuery(const SPIRV::IncomingCall *Call, Register IndexRegister = Call->Arguments[0]; const unsigned ResultWidth = Call->ReturnType->getOperand(1).getImm(); const unsigned PointerSize = GR->getPointerSize(); - const SPIRVType *PointerSizeType = + const SPIRVTypeInst PointerSizeType = GR->getOrCreateSPIRVIntegerType(PointerSize, MIRBuilder); MachineRegisterInfo *MRI = MIRBuilder.getMRI(); auto IndexInstruction = getDefInstrMaybeConstant(IndexRegister, MRI); @@ -1955,16 +1954,16 @@ static bool generateICarryBorrowInst(const SPIRV::IncomingCall *Call, SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode; Register SRetReg = Call->Arguments[0]; - SPIRVType *PtrRetType = GR->getSPIRVTypeForVReg(SRetReg); - SPIRVType *RetType = GR->getPointeeType(PtrRetType); + SPIRVTypeInst PtrRetType = GR->getSPIRVTypeForVReg(SRetReg); + SPIRVTypeInst RetType = GR->getPointeeType(PtrRetType); if (!RetType) report_fatal_error("The first parameter must be a pointer"); if (RetType->getOpcode() != SPIRV::OpTypeStruct) report_fatal_error("Expected struct type result for the arithmetic with " "overflow builtins"); - SPIRVType *OpType1 = GR->getSPIRVTypeForVReg(Call->Arguments[1]); - SPIRVType *OpType2 = GR->getSPIRVTypeForVReg(Call->Arguments[2]); + SPIRVTypeInst OpType1 = GR->getSPIRVTypeForVReg(Call->Arguments[1]); + SPIRVTypeInst OpType2 = GR->getSPIRVTypeForVReg(Call->Arguments[2]); if (!OpType1 || !OpType2 || OpType1 != OpType2) report_fatal_error("Operands must have the same type"); if (OpType1->getOpcode() == SPIRV::OpTypeVector) @@ -2024,10 +2023,10 @@ static bool generateImageSizeQueryInst(const SPIRV::IncomingCall *Call, ? Call->ReturnType->getOperand(2).getImm() : 1; // Get the actual number of query result/size components. - SPIRVType *ImgType = GR->getSPIRVTypeForVReg(Call->Arguments[0]); + SPIRVTypeInst ImgType = GR->getSPIRVTypeForVReg(Call->Arguments[0]); unsigned NumActualRetComponents = getNumSizeComponents(ImgType); Register QueryResult = Call->ReturnRegister; - SPIRVType *QueryResultType = Call->ReturnType; + SPIRVTypeInst QueryResultType = Call->ReturnType; if (NumExpectedRetComponents != NumActualRetComponents) { unsigned Bitwidth = Call->ReturnType->getOpcode() == SPIRV::OpTypeInt ? Call->ReturnType->getOperand(1).getImm() @@ -2035,7 +2034,7 @@ static bool generateImageSizeQueryInst(const SPIRV::IncomingCall *Call, QueryResult = MIRBuilder.getMRI()->createGenericVirtualRegister( LLT::fixed_vector(NumActualRetComponents, Bitwidth)); MIRBuilder.getMRI()->setRegClass(QueryResult, &SPIRV::vIDRegClass); - SPIRVType *IntTy = GR->getOrCreateSPIRVIntegerType(Bitwidth, MIRBuilder); + SPIRVTypeInst IntTy = GR->getOrCreateSPIRVIntegerType(Bitwidth, MIRBuilder); QueryResultType = GR->getOrCreateSPIRVVectorType( IntTy, NumActualRetComponents, MIRBuilder, true); GR->assignSPIRVTypeToVReg(QueryResultType, QueryResult, MIRBuilder.getMF()); @@ -2058,11 +2057,11 @@ static bool generateImageSizeQueryInst(const SPIRV::IncomingCall *Call, assert(ExtractedComposite < NumActualRetComponents && "Invalid composite index!"); Register TypeReg = GR->getSPIRVTypeID(Call->ReturnType); - SPIRVType *NewType = nullptr; + SPIRVTypeInst NewType = nullptr; if (QueryResultType->getOpcode() == SPIRV::OpTypeVector) { Register NewTypeReg = QueryResultType->getOperand(1).getReg(); if (TypeReg != NewTypeReg && - (NewType = GR->getSPIRVTypeForVReg(NewTypeReg)) != nullptr) + (NewType = GR->getSPIRVTypeForVReg(NewTypeReg))) TypeReg = NewTypeReg; } MIRBuilder.buildInstr(SPIRV::OpCompositeExtract) @@ -2070,7 +2069,7 @@ static bool generateImageSizeQueryInst(const SPIRV::IncomingCall *Call, .addUse(TypeReg) .addUse(QueryResult) .addImm(ExtractedComposite); - if (NewType != nullptr) + if (NewType) updateRegType(Call->ReturnRegister, nullptr, NewType, GR, MIRBuilder, MIRBuilder.getMF().getRegInfo()); } else { @@ -2177,8 +2176,8 @@ static bool generateReadImageInst(const StringRef DemangledCall, getSamplerParamFromBitmask(SamplerMask), getSamplerFilterModeFromBitmask(SamplerMask), MIRBuilder); } - SPIRVType *ImageType = GR->getSPIRVTypeForVReg(Image); - SPIRVType *SampledImageType = + SPIRVTypeInst ImageType = GR->getSPIRVTypeForVReg(Image); + SPIRVTypeInst SampledImageType = GR->getOrCreateOpTypeSampledImage(ImageType, MIRBuilder); Register SampledImage = MRI->createVirtualRegister(&SPIRV::iIDRegClass); @@ -2192,7 +2191,7 @@ static bool generateReadImageInst(const StringRef DemangledCall, MIRBuilder); if (Call->ReturnType->getOpcode() != SPIRV::OpTypeVector) { - SPIRVType *TempType = + SPIRVTypeInst TempType = GR->getOrCreateSPIRVVectorType(Call->ReturnType, 4, MIRBuilder, true); Register TempRegister = MRI->createGenericVirtualRegister(GR->getRegType(TempType)); @@ -2267,8 +2266,8 @@ static bool generateSampleImageInst(const StringRef DemangledCall, } else if (Call->Builtin->Name.contains_insensitive("__spirv_SampledImage")) { // Create OpSampledImage. Register Image = Call->Arguments[0]; - SPIRVType *ImageType = GR->getSPIRVTypeForVReg(Image); - SPIRVType *SampledImageType = + SPIRVTypeInst ImageType = GR->getSPIRVTypeForVReg(Image); + SPIRVTypeInst SampledImageType = GR->getOrCreateOpTypeSampledImage(ImageType, MIRBuilder); Register SampledImage = Call->ReturnRegister.isValid() @@ -2288,10 +2287,10 @@ static bool generateSampleImageInst(const StringRef DemangledCall, ReturnType = ReturnType.substr(ReturnType.find("_R") + 2); ReturnType = ReturnType.substr(0, ReturnType.find('(')); } - SPIRVType *Type = - Call->ReturnType - ? Call->ReturnType - : GR->getOrCreateSPIRVTypeByName(ReturnType, MIRBuilder, true); + SPIRVTypeInst Type = Call->ReturnType + ? Call->ReturnType + : SPIRVTypeInst(GR->getOrCreateSPIRVTypeByName( + ReturnType, MIRBuilder, true)); if (!Type) { std::string DiagMsg = "Unable to recognize SPIRV type name: " + ReturnType; @@ -2379,7 +2378,7 @@ static bool generateCoopMatrInst(const SPIRV::IncomingCall *Call, ImmArgs.push_back(getConstFromIntrinsic(Call->Arguments[LiteralIdx], MRI)); Register TypeReg = GR->getSPIRVTypeID(Call->ReturnType); if (Opcode == SPIRV::OpCooperativeMatrixLengthKHR) { - SPIRVType *CoopMatrType = GR->getSPIRVTypeForVReg(Call->Arguments[0]); + SPIRVTypeInst CoopMatrType = GR->getSPIRVTypeForVReg(Call->Arguments[0]); if (!CoopMatrType) report_fatal_error("Can't find a register's type definition"); MIRBuilder.buildInstr(Opcode) @@ -2490,7 +2489,7 @@ static bool buildAPFixedPointInst(const SPIRV::IncomingCall *Call, if (IsSRet) { const LLT ValTy = MRI->getType(InputReg); Register ActualRetValReg = MRI->createGenericVirtualRegister(ValTy); - SPIRVType *InstructionType = + SPIRVTypeInst InstructionType = GR->getPointeeType(GR->getSPIRVTypeForVReg(InputReg)); InputReg = Call->Arguments[1]; auto InputType = GR->getTypeForSPIRVType(GR->getSPIRVTypeForVReg(InputReg)); @@ -2498,7 +2497,7 @@ static bool buildAPFixedPointInst(const SPIRV::IncomingCall *Call, if (InputType->getTypeID() == llvm::Type::TypeID::TypedPointerTyID) { LLT InputLLT = MRI->getType(InputReg); PtrInputReg = MRI->createGenericVirtualRegister(InputLLT); - SPIRVType *PtrType = + SPIRVTypeInst PtrType = GR->getPointeeType(GR->getSPIRVTypeForVReg(InputReg)); MachineMemOperand *MMO1 = MIRBuilder.getMF().getMachineMemOperand( MachinePointerInfo(), MachineMemOperand::MOLoad, @@ -2621,11 +2620,11 @@ static bool buildNDRange(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR) { MachineRegisterInfo *MRI = MIRBuilder.getMRI(); - SPIRVType *PtrType = GR->getSPIRVTypeForVReg(Call->Arguments[0]); + SPIRVTypeInst PtrType = GR->getSPIRVTypeForVReg(Call->Arguments[0]); assert(PtrType->getOpcode() == SPIRV::OpTypePointer && PtrType->getOperand(2).isReg()); Register TypeReg = PtrType->getOperand(2).getReg(); - SPIRVType *StructType = GR->getSPIRVTypeForVReg(TypeReg); + SPIRVTypeInst StructType = GR->getSPIRVTypeForVReg(TypeReg); MachineFunction &MF = MIRBuilder.getMF(); Register TmpReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass); GR->assignSPIRVTypeToVReg(StructType, TmpReg, MF); @@ -2639,7 +2638,7 @@ static bool buildNDRange(const SPIRV::IncomingCall *Call, Register GlobalWorkOffset = NumArgs <= 3 ? Register(0) : Call->Arguments[1]; if (NumArgs < 4) { Register Const; - SPIRVType *SpvTy = GR->getSPIRVTypeForVReg(GlobalWorkSize); + SPIRVTypeInst SpvTy = GR->getSPIRVTypeForVReg(GlobalWorkSize); if (SpvTy->getOpcode() == SPIRV::OpTypePointer) { MachineInstr *DefInstr = MRI->getUniqueVRegDef(GlobalWorkSize); assert(DefInstr && isSpvIntrinsic(*DefInstr, Intrinsic::spv_gep) && @@ -2650,7 +2649,7 @@ static bool buildNDRange(const SPIRV::IncomingCall *Call, unsigned BitWidth = GR->getPointerSize() == 64 ? 64 : 32; Type *BaseTy = IntegerType::get(MF.getFunction().getContext(), BitWidth); Type *FieldTy = ArrayType::get(BaseTy, Size); - SPIRVType *SpvFieldTy = GR->getOrCreateSPIRVType( + SPIRVTypeInst SpvFieldTy = GR->getOrCreateSPIRVType( FieldTy, MIRBuilder, SPIRV::AccessQualifier::ReadWrite, true); GlobalWorkSize = MRI->createVirtualRegister(&SPIRV::iIDRegClass); GR->assignSPIRVTypeToVReg(SpvFieldTy, GlobalWorkSize, MF); @@ -2683,7 +2682,7 @@ static bool buildNDRange(const SPIRV::IncomingCall *Call, } // TODO: maybe move to the global register. -static SPIRVType * +static SPIRVTypeInst getOrC... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/180721 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
