================
@@ -133,23 +145,116 @@ bool AMDGPURegBankCombinerImpl::isVgprRegBank(Register
Reg) const {
return RBI.getRegBank(Reg, MRI, TRI)->getID() == AMDGPU::VGPRRegBankID;
}
+bool AMDGPURegBankCombinerImpl::isSgprRegBank(Register Reg) const {
+ return RBI.getRegBank(Reg, MRI, TRI)->getID() == AMDGPU::SGPRRegBankID;
+}
+
Register AMDGPURegBankCombinerImpl::getAsVgpr(Register Reg) const {
if (isVgprRegBank(Reg))
return Reg;
+ const RegisterBank &VgprRB = RBI.getRegBank(AMDGPU::VGPRRegBankID);
+
+ // Build constants directly in VGPR instead of copying from SGPR.
+ if (auto V = getIConstantVRegValWithLookThrough(Reg, MRI)) {
+ auto VgprCst = B.buildConstant(MRI.getType(Reg), V->Value);
+ MRI.setRegBank(VgprCst.getReg(0), VgprRB);
+ return VgprCst.getReg(0);
+ }
+ if (auto V = getFConstantVRegValWithLookThrough(Reg, MRI)) {
+ if (MRI.getType(Reg).getSizeInBits() >= 32) {
+ auto VgprCst = B.buildFConstant(MRI.getType(Reg), V->Value);
+ MRI.setRegBank(VgprCst.getReg(0), VgprRB);
+ return VgprCst.getReg(0);
+ }
+ }
+
+ // Look through READANYLANE: the VGPR source holds the same uniform value.
+ if (const MachineInstr *Def = MRI.getVRegDef(Reg)) {
+ if (Def->getOpcode() == AMDGPU::G_AMDGPU_READANYLANE) {
+ Register Src = Def->getOperand(1).getReg();
+ if (isVgprRegBank(Src))
+ return Src;
+ }
+ }
+
// Search for existing copy of Reg to vgpr.
- for (MachineInstr &Use : MRI.use_instructions(Reg)) {
+ for (MachineInstr &Use : MRI.use_nodbg_instructions(Reg)) {
Register Def = Use.getOperand(0).getReg();
if (Use.getOpcode() == AMDGPU::COPY && isVgprRegBank(Def))
return Def;
----------------
petar-avramovic wrote:
Could it be that you get Def to be defined after MI, so you end up using before
def?
https://github.com/llvm/llvm-project/pull/179352
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