================
@@ -83,13 +84,39 @@
WebAssemblyInstructionSelector::WebAssemblyInstructionSelector(
{
}
+bool WebAssemblyInstructionSelector::selectCopy(
+ MachineInstr &I, MachineRegisterInfo &MRI) const {
+ const TargetRegisterClass *DstRC =
+ TRI.getConstrainedRegClassForOperand(I.getOperand(0), MRI);
+ if (!DstRC)
+ return false;
+
+ const TargetRegisterClass *SrcRC =
+ TRI.getConstrainedRegClassForOperand(I.getOperand(1), MRI);
+ if (!SrcRC)
+ return false;
+
+ if (DstRC != SrcRC)
+ return false;
+
+ if (I.getOperand(0).getReg().isVirtual())
+ MRI.setRegClass(I.getOperand(0).getReg(), DstRC);
+ if (I.getOperand(1).getReg().isVirtual())
+ MRI.setRegClass(I.getOperand(1).getReg(), SrcRC);
----------------
arsenm wrote:
RBI.constrainGenericRegister(DstReg, *RC, *MRI)?
https://github.com/llvm/llvm-project/pull/197256
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