https://github.com/c-rhodes updated https://github.com/llvm/llvm-project/pull/198704
>From 6e5effc4990b9cf475180a46b8d08c7db391cd83 Mon Sep 17 00:00:00 2001 From: hev <[email protected]> Date: Wed, 20 May 2026 09:09:52 +0800 Subject: [PATCH] [LoongArch] Revert "Add patterns to support vector type average instructions generation" (#198306) Fixes #198254 --- .../LoongArch/LoongArchLASXInstrInfo.td | 18 - .../Target/LoongArch/LoongArchLSXInstrInfo.td | 30 -- .../LoongArch/lasx/ir-instruction/avg.ll | 321 ------------------ .../LoongArch/lsx/ir-instruction/avg.ll | 321 ------------------ 4 files changed, 690 deletions(-) delete mode 100644 llvm/test/CodeGen/LoongArch/lasx/ir-instruction/avg.ll delete mode 100644 llvm/test/CodeGen/LoongArch/lsx/ir-instruction/avg.ll diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td index fa4b720e7ba98..d539781dc63eb 100644 --- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td @@ -2037,24 +2037,6 @@ def : Pat<(v4i32(fp_to_uint v4f64:$vj)), (XVFTINTRZ_LU_D v4f64:$vj)), sub_128)>; -// XVAVG_{B/H/W/D/BU/HU/WU/DU}, XVAVGR_{B/H/W/D/BU/HU/WU/DU} -defm : VAvgPat<sra, "XVAVG_B", v32i8>; -defm : VAvgPat<sra, "XVAVG_H", v16i16>; -defm : VAvgPat<sra, "XVAVG_W", v8i32>; -defm : VAvgPat<sra, "XVAVG_D", v4i64>; -defm : VAvgPat<srl, "XVAVG_BU", v32i8>; -defm : VAvgPat<srl, "XVAVG_HU", v16i16>; -defm : VAvgPat<srl, "XVAVG_WU", v8i32>; -defm : VAvgPat<srl, "XVAVG_DU", v4i64>; -defm : VAvgrPat<sra, "XVAVGR_B", v32i8>; -defm : VAvgrPat<sra, "XVAVGR_H", v16i16>; -defm : VAvgrPat<sra, "XVAVGR_W", v8i32>; -defm : VAvgrPat<sra, "XVAVGR_D", v4i64>; -defm : VAvgrPat<srl, "XVAVGR_BU", v32i8>; -defm : VAvgrPat<srl, "XVAVGR_HU", v16i16>; -defm : VAvgrPat<srl, "XVAVGR_WU", v8i32>; -defm : VAvgrPat<srl, "XVAVGR_DU", v4i64>; - // abs def : Pat<(abs v32i8:$xj), (XVSIGNCOV_B v32i8:$xj, v32i8:$xj)>; def : Pat<(abs v16i16:$xj), (XVSIGNCOV_H v16i16:$xj, v16i16:$xj)>; diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td index da7b6e833c996..1336e751ed355 100644 --- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td @@ -1530,18 +1530,6 @@ multiclass InsertExtractPatV2<ValueType vecty, ValueType elemty> { } } -multiclass VAvgPat<SDPatternOperator OpNode, string Inst, ValueType vt> { - def : Pat<(OpNode (vt (add vt:$vj, vt:$vk)), (vt (vsplat_imm_eq_1))), - (!cast<LAInst>(Inst) vt:$vj, vt:$vk)>; -} - -multiclass VAvgrPat<SDPatternOperator OpNode, string Inst, ValueType vt> { - def : Pat<(OpNode (vt (add (vt (add vt:$vj, vt:$vk)), - (vt (vsplat_imm_eq_1)))), - (vt (vsplat_imm_eq_1))), - (!cast<LAInst>(Inst) vt:$vj, vt:$vk)>; -} - let Predicates = [HasExtLSX] in { // VADD_{B/H/W/D} @@ -2187,24 +2175,6 @@ def : Pat<(f32 f32imm_vldi:$in), def : Pat<(f64 f64imm_vldi:$in), (f64 (EXTRACT_SUBREG (VLDI (to_f64imm_vldi f64imm_vldi:$in)), sub_64))>; -// VAVG_{B/H/W/D/BU/HU/WU/DU}, VAVGR_{B/H/W/D/BU/HU/WU/DU} -defm : VAvgPat<sra, "VAVG_B", v16i8>; -defm : VAvgPat<sra, "VAVG_H", v8i16>; -defm : VAvgPat<sra, "VAVG_W", v4i32>; -defm : VAvgPat<sra, "VAVG_D", v2i64>; -defm : VAvgPat<srl, "VAVG_BU", v16i8>; -defm : VAvgPat<srl, "VAVG_HU", v8i16>; -defm : VAvgPat<srl, "VAVG_WU", v4i32>; -defm : VAvgPat<srl, "VAVG_DU", v2i64>; -defm : VAvgrPat<sra, "VAVGR_B", v16i8>; -defm : VAvgrPat<sra, "VAVGR_H", v8i16>; -defm : VAvgrPat<sra, "VAVGR_W", v4i32>; -defm : VAvgrPat<sra, "VAVGR_D", v2i64>; -defm : VAvgrPat<srl, "VAVGR_BU", v16i8>; -defm : VAvgrPat<srl, "VAVGR_HU", v8i16>; -defm : VAvgrPat<srl, "VAVGR_WU", v4i32>; -defm : VAvgrPat<srl, "VAVGR_DU", v2i64>; - // abs def : Pat<(abs v16i8:$vj), (VSIGNCOV_B v16i8:$vj, v16i8:$vj)>; def : Pat<(abs v8i16:$vj), (VSIGNCOV_H v8i16:$vj, v8i16:$vj)>; diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/avg.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/avg.ll deleted file mode 100644 index 5c5c19935080b..0000000000000 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/avg.ll +++ /dev/null @@ -1,321 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32 -; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64 - -define void @xvavg_b(ptr %res, ptr %a, ptr %b) nounwind { -; CHECK-LABEL: xvavg_b: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a1, 0 -; CHECK-NEXT: xvld $xr1, $a2, 0 -; CHECK-NEXT: xvavg.b $xr0, $xr0, $xr1 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret -entry: - %va = load <32 x i8>, ptr %a - %vb = load <32 x i8>, ptr %b - %add = add <32 x i8> %va, %vb - %shr = ashr <32 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> - store <32 x i8> %shr, ptr %res - ret void -} - -define void @xvavg_h(ptr %res, ptr %a, ptr %b) nounwind { -; CHECK-LABEL: xvavg_h: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a1, 0 -; CHECK-NEXT: xvld $xr1, $a2, 0 -; CHECK-NEXT: xvavg.h $xr0, $xr0, $xr1 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret -entry: - %va = load <16 x i16>, ptr %a - %vb = load <16 x i16>, ptr %b - %add = add <16 x i16> %va, %vb - %shr = ashr <16 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> - store <16 x i16> %shr, ptr %res - ret void -} - -define void @xvavg_w(ptr %res, ptr %a, ptr %b) nounwind { -; CHECK-LABEL: xvavg_w: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a1, 0 -; CHECK-NEXT: xvld $xr1, $a2, 0 -; CHECK-NEXT: xvavg.w $xr0, $xr0, $xr1 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret -entry: - %va = load <8 x i32>, ptr %a - %vb = load <8 x i32>, ptr %b - %add = add <8 x i32> %va, %vb - %shr = ashr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> - store <8 x i32> %shr, ptr %res - ret void -} - -define void @xvavg_d(ptr %res, ptr %a, ptr %b) nounwind { -; LA32-LABEL: xvavg_d: -; LA32: # %bb.0: # %entry -; LA32-NEXT: xvld $xr0, $a1, 0 -; LA32-NEXT: xvld $xr1, $a2, 0 -; LA32-NEXT: xvadd.d $xr0, $xr0, $xr1 -; LA32-NEXT: xvsrai.d $xr0, $xr0, 1 -; LA32-NEXT: xvst $xr0, $a0, 0 -; LA32-NEXT: ret -; -; LA64-LABEL: xvavg_d: -; LA64: # %bb.0: # %entry -; LA64-NEXT: xvld $xr0, $a1, 0 -; LA64-NEXT: xvld $xr1, $a2, 0 -; LA64-NEXT: xvavg.d $xr0, $xr0, $xr1 -; LA64-NEXT: xvst $xr0, $a0, 0 -; LA64-NEXT: ret -entry: - %va = load <4 x i64>, ptr %a - %vb = load <4 x i64>, ptr %b - %add = add <4 x i64> %va, %vb - %shr = ashr <4 x i64> %add, <i64 1, i64 1, i64 1, i64 1> - store <4 x i64> %shr, ptr %res - ret void -} - -define void @xvavg_bu(ptr %res, ptr %a, ptr %b) nounwind { -; CHECK-LABEL: xvavg_bu: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a1, 0 -; CHECK-NEXT: xvld $xr1, $a2, 0 -; CHECK-NEXT: xvavg.bu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret -entry: - %va = load <32 x i8>, ptr %a - %vb = load <32 x i8>, ptr %b - %add = add <32 x i8> %va, %vb - %shr = lshr <32 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> - store <32 x i8> %shr, ptr %res - ret void -} - -define void @xvavg_hu(ptr %res, ptr %a, ptr %b) nounwind { -; CHECK-LABEL: xvavg_hu: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a1, 0 -; CHECK-NEXT: xvld $xr1, $a2, 0 -; CHECK-NEXT: xvavg.hu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret -entry: - %va = load <16 x i16>, ptr %a - %vb = load <16 x i16>, ptr %b - %add = add <16 x i16> %va, %vb - %shr = lshr <16 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> - store <16 x i16> %shr, ptr %res - ret void -} - -define void @xvavg_wu(ptr %res, ptr %a, ptr %b) nounwind { -; CHECK-LABEL: xvavg_wu: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a1, 0 -; CHECK-NEXT: xvld $xr1, $a2, 0 -; CHECK-NEXT: xvavg.wu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret -entry: - %va = load <8 x i32>, ptr %a - %vb = load <8 x i32>, ptr %b - %add = add <8 x i32> %va, %vb - %shr = lshr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> - store <8 x i32> %shr, ptr %res - ret void -} - -define void @xvavg_du(ptr %res, ptr %a, ptr %b) nounwind { -; LA32-LABEL: xvavg_du: -; LA32: # %bb.0: # %entry -; LA32-NEXT: xvld $xr0, $a1, 0 -; LA32-NEXT: xvld $xr1, $a2, 0 -; LA32-NEXT: xvadd.d $xr0, $xr0, $xr1 -; LA32-NEXT: xvsrli.d $xr0, $xr0, 1 -; LA32-NEXT: xvst $xr0, $a0, 0 -; LA32-NEXT: ret -; -; LA64-LABEL: xvavg_du: -; LA64: # %bb.0: # %entry -; LA64-NEXT: xvld $xr0, $a1, 0 -; LA64-NEXT: xvld $xr1, $a2, 0 -; LA64-NEXT: xvavg.du $xr0, $xr0, $xr1 -; LA64-NEXT: xvst $xr0, $a0, 0 -; LA64-NEXT: ret -entry: - %va = load <4 x i64>, ptr %a - %vb = load <4 x i64>, ptr %b - %add = add <4 x i64> %va, %vb - %shr = lshr <4 x i64> %add, <i64 1, i64 1, i64 1, i64 1> - store <4 x i64> %shr, ptr %res - ret void -} - -define void @xvavgr_b(ptr %res, ptr %a, ptr %b) nounwind { -; CHECK-LABEL: xvavgr_b: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a1, 0 -; CHECK-NEXT: xvld $xr1, $a2, 0 -; CHECK-NEXT: xvavgr.b $xr0, $xr0, $xr1 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret -entry: - %va = load <32 x i8>, ptr %a - %vb = load <32 x i8>, ptr %b - %add = add <32 x i8> %va, %vb - %add1 = add <32 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> - %shr = ashr <32 x i8> %add1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> - store <32 x i8> %shr, ptr %res - ret void -} - -define void @xvavgr_h(ptr %res, ptr %a, ptr %b) nounwind { -; CHECK-LABEL: xvavgr_h: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a1, 0 -; CHECK-NEXT: xvld $xr1, $a2, 0 -; CHECK-NEXT: xvavgr.h $xr0, $xr0, $xr1 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret -entry: - %va = load <16 x i16>, ptr %a - %vb = load <16 x i16>, ptr %b - %add = add <16 x i16> %va, %vb - %add1 = add <16 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> - %shr = ashr <16 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> - store <16 x i16> %shr, ptr %res - ret void -} - -define void @xvavgr_w(ptr %res, ptr %a, ptr %b) nounwind { -; CHECK-LABEL: xvavgr_w: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a1, 0 -; CHECK-NEXT: xvld $xr1, $a2, 0 -; CHECK-NEXT: xvavgr.w $xr0, $xr0, $xr1 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret -entry: - %va = load <8 x i32>, ptr %a - %vb = load <8 x i32>, ptr %b - %add = add <8 x i32> %va, %vb - %add1 = add <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> - %shr = ashr <8 x i32> %add1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> - store <8 x i32> %shr, ptr %res - ret void -} - -define void @xvavgr_d(ptr %res, ptr %a, ptr %b) nounwind { -; LA32-LABEL: xvavgr_d: -; LA32: # %bb.0: # %entry -; LA32-NEXT: xvld $xr0, $a1, 0 -; LA32-NEXT: xvld $xr1, $a2, 0 -; LA32-NEXT: xvadd.d $xr0, $xr0, $xr1 -; LA32-NEXT: xvaddi.du $xr0, $xr0, 1 -; LA32-NEXT: xvsrai.d $xr0, $xr0, 1 -; LA32-NEXT: xvst $xr0, $a0, 0 -; LA32-NEXT: ret -; -; LA64-LABEL: xvavgr_d: -; LA64: # %bb.0: # %entry -; LA64-NEXT: xvld $xr0, $a1, 0 -; LA64-NEXT: xvld $xr1, $a2, 0 -; LA64-NEXT: xvavgr.d $xr0, $xr0, $xr1 -; LA64-NEXT: xvst $xr0, $a0, 0 -; LA64-NEXT: ret -entry: - %va = load <4 x i64>, ptr %a - %vb = load <4 x i64>, ptr %b - %add = add <4 x i64> %va, %vb - %add1 = add <4 x i64> %add, <i64 1, i64 1, i64 1, i64 1> - %shr = ashr <4 x i64> %add1, <i64 1, i64 1, i64 1, i64 1> - store <4 x i64> %shr, ptr %res - ret void -} - -define void @xvavgr_bu(ptr %res, ptr %a, ptr %b) nounwind { -; CHECK-LABEL: xvavgr_bu: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a1, 0 -; CHECK-NEXT: xvld $xr1, $a2, 0 -; CHECK-NEXT: xvavgr.bu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret -entry: - %va = load <32 x i8>, ptr %a - %vb = load <32 x i8>, ptr %b - %add = add <32 x i8> %va, %vb - %add1 = add <32 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> - %shr = lshr <32 x i8> %add1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> - store <32 x i8> %shr, ptr %res - ret void -} - -define void @xvavgr_hu(ptr %res, ptr %a, ptr %b) nounwind { -; CHECK-LABEL: xvavgr_hu: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a1, 0 -; CHECK-NEXT: xvld $xr1, $a2, 0 -; CHECK-NEXT: xvavgr.hu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret -entry: - %va = load <16 x i16>, ptr %a - %vb = load <16 x i16>, ptr %b - %add = add <16 x i16> %va, %vb - %add1 = add <16 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> - %shr = lshr <16 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> - store <16 x i16> %shr, ptr %res - ret void -} - -define void @xvavgr_wu(ptr %res, ptr %a, ptr %b) nounwind { -; CHECK-LABEL: xvavgr_wu: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a1, 0 -; CHECK-NEXT: xvld $xr1, $a2, 0 -; CHECK-NEXT: xvavgr.wu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret -entry: - %va = load <8 x i32>, ptr %a - %vb = load <8 x i32>, ptr %b - %add = add <8 x i32> %va, %vb - %add1 = add <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> - %shr = lshr <8 x i32> %add1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> - store <8 x i32> %shr, ptr %res - ret void -} - -define void @xvavgr_du(ptr %res, ptr %a, ptr %b) nounwind { -; LA32-LABEL: xvavgr_du: -; LA32: # %bb.0: # %entry -; LA32-NEXT: xvld $xr0, $a1, 0 -; LA32-NEXT: xvld $xr1, $a2, 0 -; LA32-NEXT: xvadd.d $xr0, $xr0, $xr1 -; LA32-NEXT: xvaddi.du $xr0, $xr0, 1 -; LA32-NEXT: xvsrli.d $xr0, $xr0, 1 -; LA32-NEXT: xvst $xr0, $a0, 0 -; LA32-NEXT: ret -; -; LA64-LABEL: xvavgr_du: -; LA64: # %bb.0: # %entry -; LA64-NEXT: xvld $xr0, $a1, 0 -; LA64-NEXT: xvld $xr1, $a2, 0 -; LA64-NEXT: xvavgr.du $xr0, $xr0, $xr1 -; LA64-NEXT: xvst $xr0, $a0, 0 -; LA64-NEXT: ret -entry: - %va = load <4 x i64>, ptr %a - %vb = load <4 x i64>, ptr %b - %add = add <4 x i64> %va, %vb - %add1 = add <4 x i64> %add, <i64 1, i64 1, i64 1, i64 1> - %shr = lshr <4 x i64> %add1, <i64 1, i64 1, i64 1, i64 1> - store <4 x i64> %shr, ptr %res - ret void -} diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/avg.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/avg.ll deleted file mode 100644 index 334af22edee59..0000000000000 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/avg.ll +++ /dev/null @@ -1,321 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32 -; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64 - -define void @vavg_b(ptr %res, ptr %a, ptr %b) nounwind { -; CHECK-LABEL: vavg_b: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vld $vr0, $a1, 0 -; CHECK-NEXT: vld $vr1, $a2, 0 -; CHECK-NEXT: vavg.b $vr0, $vr0, $vr1 -; CHECK-NEXT: vst $vr0, $a0, 0 -; CHECK-NEXT: ret -entry: - %va = load <16 x i8>, ptr %a - %vb = load <16 x i8>, ptr %b - %add = add <16 x i8> %va, %vb - %shr = ashr <16 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> - store <16 x i8> %shr, ptr %res - ret void -} - -define void @vavg_h(ptr %res, ptr %a, ptr %b) nounwind { -; CHECK-LABEL: vavg_h: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vld $vr0, $a1, 0 -; CHECK-NEXT: vld $vr1, $a2, 0 -; CHECK-NEXT: vavg.h $vr0, $vr0, $vr1 -; CHECK-NEXT: vst $vr0, $a0, 0 -; CHECK-NEXT: ret -entry: - %va = load <8 x i16>, ptr %a - %vb = load <8 x i16>, ptr %b - %add = add <8 x i16> %va, %vb - %shr = ashr <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> - store <8 x i16> %shr, ptr %res - ret void -} - -define void @vavg_w(ptr %res, ptr %a, ptr %b) nounwind { -; CHECK-LABEL: vavg_w: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vld $vr0, $a1, 0 -; CHECK-NEXT: vld $vr1, $a2, 0 -; CHECK-NEXT: vavg.w $vr0, $vr0, $vr1 -; CHECK-NEXT: vst $vr0, $a0, 0 -; CHECK-NEXT: ret -entry: - %va = load <4 x i32>, ptr %a - %vb = load <4 x i32>, ptr %b - %add = add <4 x i32> %va, %vb - %shr = ashr <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1> - store <4 x i32> %shr, ptr %res - ret void -} - -define void @vavg_d(ptr %res, ptr %a, ptr %b) nounwind { -; LA32-LABEL: vavg_d: -; LA32: # %bb.0: # %entry -; LA32-NEXT: vld $vr0, $a1, 0 -; LA32-NEXT: vld $vr1, $a2, 0 -; LA32-NEXT: vadd.d $vr0, $vr0, $vr1 -; LA32-NEXT: vsrai.d $vr0, $vr0, 1 -; LA32-NEXT: vst $vr0, $a0, 0 -; LA32-NEXT: ret -; -; LA64-LABEL: vavg_d: -; LA64: # %bb.0: # %entry -; LA64-NEXT: vld $vr0, $a1, 0 -; LA64-NEXT: vld $vr1, $a2, 0 -; LA64-NEXT: vavg.d $vr0, $vr0, $vr1 -; LA64-NEXT: vst $vr0, $a0, 0 -; LA64-NEXT: ret -entry: - %va = load <2 x i64>, ptr %a - %vb = load <2 x i64>, ptr %b - %add = add <2 x i64> %va, %vb - %shr = ashr <2 x i64> %add, <i64 1, i64 1> - store <2 x i64> %shr, ptr %res - ret void -} - -define void @vavg_bu(ptr %res, ptr %a, ptr %b) nounwind { -; CHECK-LABEL: vavg_bu: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vld $vr0, $a1, 0 -; CHECK-NEXT: vld $vr1, $a2, 0 -; CHECK-NEXT: vavg.bu $vr0, $vr0, $vr1 -; CHECK-NEXT: vst $vr0, $a0, 0 -; CHECK-NEXT: ret -entry: - %va = load <16 x i8>, ptr %a - %vb = load <16 x i8>, ptr %b - %add = add <16 x i8> %va, %vb - %shr = lshr <16 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> - store <16 x i8> %shr, ptr %res - ret void -} - -define void @vavg_hu(ptr %res, ptr %a, ptr %b) nounwind { -; CHECK-LABEL: vavg_hu: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vld $vr0, $a1, 0 -; CHECK-NEXT: vld $vr1, $a2, 0 -; CHECK-NEXT: vavg.hu $vr0, $vr0, $vr1 -; CHECK-NEXT: vst $vr0, $a0, 0 -; CHECK-NEXT: ret -entry: - %va = load <8 x i16>, ptr %a - %vb = load <8 x i16>, ptr %b - %add = add <8 x i16> %va, %vb - %shr = lshr <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> - store <8 x i16> %shr, ptr %res - ret void -} - -define void @vavg_wu(ptr %res, ptr %a, ptr %b) nounwind { -; CHECK-LABEL: vavg_wu: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vld $vr0, $a1, 0 -; CHECK-NEXT: vld $vr1, $a2, 0 -; CHECK-NEXT: vavg.wu $vr0, $vr0, $vr1 -; CHECK-NEXT: vst $vr0, $a0, 0 -; CHECK-NEXT: ret -entry: - %va = load <4 x i32>, ptr %a - %vb = load <4 x i32>, ptr %b - %add = add <4 x i32> %va, %vb - %shr = lshr <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1> - store <4 x i32> %shr, ptr %res - ret void -} - -define void @vavg_du(ptr %res, ptr %a, ptr %b) nounwind { -; LA32-LABEL: vavg_du: -; LA32: # %bb.0: # %entry -; LA32-NEXT: vld $vr0, $a1, 0 -; LA32-NEXT: vld $vr1, $a2, 0 -; LA32-NEXT: vadd.d $vr0, $vr0, $vr1 -; LA32-NEXT: vsrli.d $vr0, $vr0, 1 -; LA32-NEXT: vst $vr0, $a0, 0 -; LA32-NEXT: ret -; -; LA64-LABEL: vavg_du: -; LA64: # %bb.0: # %entry -; LA64-NEXT: vld $vr0, $a1, 0 -; LA64-NEXT: vld $vr1, $a2, 0 -; LA64-NEXT: vavg.du $vr0, $vr0, $vr1 -; LA64-NEXT: vst $vr0, $a0, 0 -; LA64-NEXT: ret -entry: - %va = load <2 x i64>, ptr %a - %vb = load <2 x i64>, ptr %b - %add = add <2 x i64> %va, %vb - %shr = lshr <2 x i64> %add, <i64 1, i64 1> - store <2 x i64> %shr, ptr %res - ret void -} - -define void @vavgr_b(ptr %res, ptr %a, ptr %b) nounwind { -; CHECK-LABEL: vavgr_b: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vld $vr0, $a1, 0 -; CHECK-NEXT: vld $vr1, $a2, 0 -; CHECK-NEXT: vavgr.b $vr0, $vr0, $vr1 -; CHECK-NEXT: vst $vr0, $a0, 0 -; CHECK-NEXT: ret -entry: - %va = load <16 x i8>, ptr %a - %vb = load <16 x i8>, ptr %b - %add = add <16 x i8> %va, %vb - %add1 = add <16 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> - %shr = ashr <16 x i8> %add1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> - store <16 x i8> %shr, ptr %res - ret void -} - -define void @vavgr_h(ptr %res, ptr %a, ptr %b) nounwind { -; CHECK-LABEL: vavgr_h: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vld $vr0, $a1, 0 -; CHECK-NEXT: vld $vr1, $a2, 0 -; CHECK-NEXT: vavgr.h $vr0, $vr0, $vr1 -; CHECK-NEXT: vst $vr0, $a0, 0 -; CHECK-NEXT: ret -entry: - %va = load <8 x i16>, ptr %a - %vb = load <8 x i16>, ptr %b - %add = add <8 x i16> %va, %vb - %add1 = add <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> - %shr = ashr <8 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> - store <8 x i16> %shr, ptr %res - ret void -} - -define void @vavgr_w(ptr %res, ptr %a, ptr %b) nounwind { -; CHECK-LABEL: vavgr_w: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vld $vr0, $a1, 0 -; CHECK-NEXT: vld $vr1, $a2, 0 -; CHECK-NEXT: vavgr.w $vr0, $vr0, $vr1 -; CHECK-NEXT: vst $vr0, $a0, 0 -; CHECK-NEXT: ret -entry: - %va = load <4 x i32>, ptr %a - %vb = load <4 x i32>, ptr %b - %add = add <4 x i32> %va, %vb - %add1 = add <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1> - %shr = ashr <4 x i32> %add1, <i32 1, i32 1, i32 1, i32 1> - store <4 x i32> %shr, ptr %res - ret void -} - -define void @vavgr_d(ptr %res, ptr %a, ptr %b) nounwind { -; LA32-LABEL: vavgr_d: -; LA32: # %bb.0: # %entry -; LA32-NEXT: vld $vr0, $a1, 0 -; LA32-NEXT: vld $vr1, $a2, 0 -; LA32-NEXT: vadd.d $vr0, $vr0, $vr1 -; LA32-NEXT: vaddi.du $vr0, $vr0, 1 -; LA32-NEXT: vsrai.d $vr0, $vr0, 1 -; LA32-NEXT: vst $vr0, $a0, 0 -; LA32-NEXT: ret -; -; LA64-LABEL: vavgr_d: -; LA64: # %bb.0: # %entry -; LA64-NEXT: vld $vr0, $a1, 0 -; LA64-NEXT: vld $vr1, $a2, 0 -; LA64-NEXT: vavgr.d $vr0, $vr0, $vr1 -; LA64-NEXT: vst $vr0, $a0, 0 -; LA64-NEXT: ret -entry: - %va = load <2 x i64>, ptr %a - %vb = load <2 x i64>, ptr %b - %add = add <2 x i64> %va, %vb - %add1 = add <2 x i64> %add, <i64 1, i64 1> - %shr = ashr <2 x i64> %add1, <i64 1, i64 1> - store <2 x i64> %shr, ptr %res - ret void -} - -define void @vavgr_bu(ptr %res, ptr %a, ptr %b) nounwind { -; CHECK-LABEL: vavgr_bu: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vld $vr0, $a1, 0 -; CHECK-NEXT: vld $vr1, $a2, 0 -; CHECK-NEXT: vavgr.bu $vr0, $vr0, $vr1 -; CHECK-NEXT: vst $vr0, $a0, 0 -; CHECK-NEXT: ret -entry: - %va = load <16 x i8>, ptr %a - %vb = load <16 x i8>, ptr %b - %add = add <16 x i8> %va, %vb - %add1 = add <16 x i8> %add, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> - %shr = lshr <16 x i8> %add1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> - store <16 x i8> %shr, ptr %res - ret void -} - -define void @vavgr_hu(ptr %res, ptr %a, ptr %b) nounwind { -; CHECK-LABEL: vavgr_hu: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vld $vr0, $a1, 0 -; CHECK-NEXT: vld $vr1, $a2, 0 -; CHECK-NEXT: vavgr.hu $vr0, $vr0, $vr1 -; CHECK-NEXT: vst $vr0, $a0, 0 -; CHECK-NEXT: ret -entry: - %va = load <8 x i16>, ptr %a - %vb = load <8 x i16>, ptr %b - %add = add <8 x i16> %va, %vb - %add1 = add <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> - %shr = lshr <8 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> - store <8 x i16> %shr, ptr %res - ret void -} - -define void @vavgr_wu(ptr %res, ptr %a, ptr %b) nounwind { -; CHECK-LABEL: vavgr_wu: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vld $vr0, $a1, 0 -; CHECK-NEXT: vld $vr1, $a2, 0 -; CHECK-NEXT: vavgr.wu $vr0, $vr0, $vr1 -; CHECK-NEXT: vst $vr0, $a0, 0 -; CHECK-NEXT: ret -entry: - %va = load <4 x i32>, ptr %a - %vb = load <4 x i32>, ptr %b - %add = add <4 x i32> %va, %vb - %add1 = add <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1> - %shr = lshr <4 x i32> %add1, <i32 1, i32 1, i32 1, i32 1> - store <4 x i32> %shr, ptr %res - ret void -} - -define void @vavgr_du(ptr %res, ptr %a, ptr %b) nounwind { -; LA32-LABEL: vavgr_du: -; LA32: # %bb.0: # %entry -; LA32-NEXT: vld $vr0, $a1, 0 -; LA32-NEXT: vld $vr1, $a2, 0 -; LA32-NEXT: vadd.d $vr0, $vr0, $vr1 -; LA32-NEXT: vaddi.du $vr0, $vr0, 1 -; LA32-NEXT: vsrli.d $vr0, $vr0, 1 -; LA32-NEXT: vst $vr0, $a0, 0 -; LA32-NEXT: ret -; -; LA64-LABEL: vavgr_du: -; LA64: # %bb.0: # %entry -; LA64-NEXT: vld $vr0, $a1, 0 -; LA64-NEXT: vld $vr1, $a2, 0 -; LA64-NEXT: vavgr.du $vr0, $vr0, $vr1 -; LA64-NEXT: vst $vr0, $a0, 0 -; LA64-NEXT: ret -entry: - %va = load <2 x i64>, ptr %a - %vb = load <2 x i64>, ptr %b - %add = add <2 x i64> %va, %vb - %add1 = add <2 x i64> %add, <i64 1, i64 1> - %shr = lshr <2 x i64> %add1, <i64 1, i64 1> - store <2 x i64> %shr, ptr %res - ret void -} _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
