================
@@ -1846,15 +1846,32 @@ def Feature32Bit
: SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">;
def Feature64Bit
: SubtargetFeature<"64bit", "IsRV64", "true", "Implements RV64">;
+// By default enabling RVY uses capability pointers, to use RVI/RVE compatible
+// integral addresses the internal +rvy-int-mode flag can be used.
+// NOTE: the final user-visible flag is still TBD, this flag only exists for
----------------
resistor wrote:
This corresponds to hybrid mode in current nomenclature, right? I don't think
we have any plans to use it on CHERIoT, so we can live with whatever name.
https://github.com/llvm/llvm-project/pull/177073
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