Author: Valery Pykhtin Date: 2026-05-29T16:33:58+02:00 New Revision: 08a7337badaaddbf4cd5c4dadf924024e2fd7429
URL: https://github.com/llvm/llvm-project/commit/08a7337badaaddbf4cd5c4dadf924024e2fd7429 DIFF: https://github.com/llvm/llvm-project/commit/08a7337badaaddbf4cd5c4dadf924024e2fd7429.diff LOG: Revert "[NFC][AMDGPU] Introduce AMDGPU::FlatVariant enum to replace uint64_t …" This reverts commit 170bdf55faef8000f8abe8eb97472b3c3bab91c5. Added: Modified: llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h llvm/lib/Target/AMDGPU/SIDefines.h llvm/lib/Target/AMDGPU/SIFrameLowering.cpp llvm/lib/Target/AMDGPU/SIISelLowering.cpp llvm/lib/Target/AMDGPU/SIInstrInfo.cpp llvm/lib/Target/AMDGPU/SIInstrInfo.h llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index b24fa05c8465a..ecf8d957fc80f 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -1865,23 +1865,22 @@ static MemSDNode* findMemSDNode(SDNode *N) { llvm_unreachable("cannot find MemSDNode in the pattern!"); } -bool AMDGPUDAGToDAGISel::SelectFlatOffsetImpl( - SDNode *N, SDValue Addr, SDValue &VAddr, SDValue &Offset, - AMDGPU::FlatVariant FlatVariant) const { - using AMDGPU::FlatVariant; +bool AMDGPUDAGToDAGISel::SelectFlatOffsetImpl(SDNode *N, SDValue Addr, + SDValue &VAddr, SDValue &Offset, + uint64_t FlatVariant) const { int64_t OffsetVal = 0; unsigned AS = findMemSDNode(N)->getAddressSpace(); bool CanHaveFlatSegmentOffsetBug = Subtarget->hasFlatSegmentOffsetBug() && - FlatVariant == FlatVariant::FLAT && + FlatVariant == SIInstrFlags::FLAT && (AS == AMDGPUAS::FLAT_ADDRESS || AS == AMDGPUAS::GLOBAL_ADDRESS); if (Subtarget->hasFlatInstOffsets() && !CanHaveFlatSegmentOffsetBug) { SDValue N0, N1; if (isBaseWithConstantOffset64(Addr, N0, N1) && - (FlatVariant != FlatVariant::FlatScratch || + (FlatVariant != SIInstrFlags::FlatScratch || isFlatScratchBaseLegal(Addr))) { int64_t COffsetVal = cast<ConstantSDNode>(N1)->getSExtValue(); @@ -1890,7 +1889,7 @@ bool AMDGPUDAGToDAGISel::SelectFlatOffsetImpl( // only fold offsets from inbounds GEPs into FLAT instructions. bool IsInBounds = Addr.getOpcode() == ISD::PTRADD && Addr->getFlags().hasInBounds(); - if (COffsetVal == 0 || FlatVariant != FlatVariant::FLAT || IsInBounds) { + if (COffsetVal == 0 || FlatVariant != SIInstrFlags::FLAT || IsInBounds) { const SIInstrInfo *TII = Subtarget->getInstrInfo(); if (TII->isLegalFLATOffset(COffsetVal, AS, FlatVariant)) { Addr = N0; @@ -1975,22 +1974,20 @@ bool AMDGPUDAGToDAGISel::SelectFlatOffsetImpl( bool AMDGPUDAGToDAGISel::SelectFlatOffset(SDNode *N, SDValue Addr, SDValue &VAddr, SDValue &Offset) const { - return SelectFlatOffsetImpl(N, Addr, VAddr, Offset, - AMDGPU::FlatVariant::FLAT); + return SelectFlatOffsetImpl(N, Addr, VAddr, Offset, SIInstrFlags::FLAT); } bool AMDGPUDAGToDAGISel::SelectGlobalOffset(SDNode *N, SDValue Addr, SDValue &VAddr, SDValue &Offset) const { - return SelectFlatOffsetImpl(N, Addr, VAddr, Offset, - AMDGPU::FlatVariant::FlatGlobal); + return SelectFlatOffsetImpl(N, Addr, VAddr, Offset, SIInstrFlags::FlatGlobal); } bool AMDGPUDAGToDAGISel::SelectScratchOffset(SDNode *N, SDValue Addr, SDValue &VAddr, SDValue &Offset) const { return SelectFlatOffsetImpl(N, Addr, VAddr, Offset, - AMDGPU::FlatVariant::FlatScratch); + SIInstrFlags::FlatScratch); } // If this matches *_extend i32:x, return x @@ -2016,7 +2013,6 @@ bool AMDGPUDAGToDAGISel::SelectGlobalSAddr(SDNode *N, SDValue Addr, SDValue &SAddr, SDValue &VOffset, SDValue &Offset, bool &ScaleOffset, bool NeedIOffset) const { - using AMDGPU::FlatVariant; int64_t ImmOffset = 0; ScaleOffset = false; @@ -2030,7 +2026,7 @@ bool AMDGPUDAGToDAGISel::SelectGlobalSAddr(SDNode *N, SDValue Addr, if (NeedIOffset && TII->isLegalFLATOffset(COffsetVal, AMDGPUAS::GLOBAL_ADDRESS, - FlatVariant::FlatGlobal)) { + SIInstrFlags::FlatGlobal)) { Addr = LHS; ImmOffset = COffsetVal; } else if (!LHS->isDivergent()) { @@ -2042,7 +2038,7 @@ bool AMDGPUDAGToDAGISel::SelectGlobalSAddr(SDNode *N, SDValue Addr, int64_t SplitImmOffset = 0, RemainderOffset = COffsetVal; if (NeedIOffset) { std::tie(SplitImmOffset, RemainderOffset) = TII->splitFlatOffset( - COffsetVal, AMDGPUAS::GLOBAL_ADDRESS, FlatVariant::FlatGlobal); + COffsetVal, AMDGPUAS::GLOBAL_ADDRESS, SIInstrFlags::FlatGlobal); } if (Subtarget->hasSignedGVSOffset() ? isInt<32>(RemainderOffset) @@ -2255,7 +2251,6 @@ static SDValue SelectSAddrFI(SelectionDAG *CurDAG, SDValue SAddr) { bool AMDGPUDAGToDAGISel::SelectScratchSAddr(SDNode *Parent, SDValue Addr, SDValue &SAddr, SDValue &Offset) const { - using AMDGPU::FlatVariant; if (Addr->isDivergent()) return false; @@ -2275,10 +2270,10 @@ bool AMDGPUDAGToDAGISel::SelectScratchSAddr(SDNode *Parent, SDValue Addr, const SIInstrInfo *TII = Subtarget->getInstrInfo(); if (!TII->isLegalFLATOffset(COffsetVal, AMDGPUAS::PRIVATE_ADDRESS, - FlatVariant::FlatScratch)) { + SIInstrFlags::FlatScratch)) { int64_t SplitImmOffset, RemainderOffset; std::tie(SplitImmOffset, RemainderOffset) = TII->splitFlatOffset( - COffsetVal, AMDGPUAS::PRIVATE_ADDRESS, FlatVariant::FlatScratch); + COffsetVal, AMDGPUAS::PRIVATE_ADDRESS, SIInstrFlags::FlatScratch); COffsetVal = SplitImmOffset; @@ -2328,7 +2323,7 @@ bool AMDGPUDAGToDAGISel::SelectScratchSVAddr(SDNode *N, SDValue Addr, const SIInstrInfo *TII = Subtarget->getInstrInfo(); if (TII->isLegalFLATOffset(COffsetVal, AMDGPUAS::PRIVATE_ADDRESS, - AMDGPU::FlatVariant::FlatScratch)) { + SIInstrFlags::FlatScratch)) { Addr = LHS; ImmOffset = COffsetVal; } else if (!LHS->isDivergent() && COffsetVal > 0) { @@ -2336,9 +2331,8 @@ bool AMDGPUDAGToDAGISel::SelectScratchSVAddr(SDNode *N, SDValue Addr, // saddr + large_offset -> saddr + (vaddr = large_offset & ~MaxOffset) + // (large_offset & MaxOffset); int64_t SplitImmOffset, RemainderOffset; - std::tie(SplitImmOffset, RemainderOffset) = - TII->splitFlatOffset(COffsetVal, AMDGPUAS::PRIVATE_ADDRESS, - AMDGPU::FlatVariant::FlatScratch); + std::tie(SplitImmOffset, RemainderOffset) = TII->splitFlatOffset( + COffsetVal, AMDGPUAS::PRIVATE_ADDRESS, SIInstrFlags::FlatScratch); if (isUInt<32>(RemainderOffset)) { SDNode *VMov = CurDAG->getMachineNode( diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h index 646761a9f2406..0a3631e4dbf59 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h @@ -155,8 +155,7 @@ class AMDGPUDAGToDAGISel : public SelectionDAGISel { bool SelectBUFSOffset(SDValue Addr, SDValue &SOffset) const; bool SelectFlatOffsetImpl(SDNode *N, SDValue Addr, SDValue &VAddr, - SDValue &Offset, - AMDGPU::FlatVariant FlatVariant) const; + SDValue &Offset, uint64_t FlatVariant) const; bool SelectFlatOffset(SDNode *N, SDValue Addr, SDValue &VAddr, SDValue &Offset) const; bool SelectGlobalOffset(SDNode *N, SDValue Addr, SDValue &VAddr, diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index c8dbe14701744..4ca2de216f487 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -5869,8 +5869,9 @@ AMDGPUInstructionSelector::selectSmrdSgprImm(MachineOperand &Root) const { [=](MachineInstrBuilder &MIB) { MIB.addImm(CPol); }}}; } -std::pair<Register, int> AMDGPUInstructionSelector::selectFlatOffsetImpl( - MachineOperand &Root, AMDGPU::FlatVariant FlatVariant) const { +std::pair<Register, int> +AMDGPUInstructionSelector::selectFlatOffsetImpl(MachineOperand &Root, + uint64_t FlatVariant) const { MachineInstr *MI = Root.getParent(); auto Default = std::pair(Root.getReg(), 0); @@ -5889,9 +5890,9 @@ std::pair<Register, int> AMDGPUInstructionSelector::selectFlatOffsetImpl( // Therefore we can only fold offsets from inbounds GEPs into FLAT // instructions. if (ConstOffset == 0 || - (FlatVariant == AMDGPU::FlatVariant::FlatScratch && + (FlatVariant == SIInstrFlags::FlatScratch && !isFlatScratchBaseLegal(Root.getReg())) || - (FlatVariant == AMDGPU::FlatVariant::FLAT && !IsInBounds)) + (FlatVariant == SIInstrFlags::FLAT && !IsInBounds)) return Default; unsigned AddrSpace = (*MI->memoperands_begin())->getAddrSpace(); @@ -5903,7 +5904,7 @@ std::pair<Register, int> AMDGPUInstructionSelector::selectFlatOffsetImpl( InstructionSelector::ComplexRendererFns AMDGPUInstructionSelector::selectFlatOffset(MachineOperand &Root) const { - auto PtrWithOffset = selectFlatOffsetImpl(Root, AMDGPU::FlatVariant::FLAT); + auto PtrWithOffset = selectFlatOffsetImpl(Root, SIInstrFlags::FLAT); return {{ [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); }, @@ -5913,8 +5914,7 @@ AMDGPUInstructionSelector::selectFlatOffset(MachineOperand &Root) const { InstructionSelector::ComplexRendererFns AMDGPUInstructionSelector::selectGlobalOffset(MachineOperand &Root) const { - auto PtrWithOffset = - selectFlatOffsetImpl(Root, AMDGPU::FlatVariant::FlatGlobal); + auto PtrWithOffset = selectFlatOffsetImpl(Root, SIInstrFlags::FlatGlobal); return {{ [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); }, @@ -5924,8 +5924,7 @@ AMDGPUInstructionSelector::selectGlobalOffset(MachineOperand &Root) const { InstructionSelector::ComplexRendererFns AMDGPUInstructionSelector::selectScratchOffset(MachineOperand &Root) const { - auto PtrWithOffset = - selectFlatOffsetImpl(Root, AMDGPU::FlatVariant::FlatScratch); + auto PtrWithOffset = selectFlatOffsetImpl(Root, SIInstrFlags::FlatScratch); return {{ [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); }, @@ -5951,7 +5950,7 @@ AMDGPUInstructionSelector::selectGlobalSAddr(MachineOperand &Root, if (ConstOffset != 0) { if (NeedIOffset && TII.isLegalFLATOffset(ConstOffset, AMDGPUAS::GLOBAL_ADDRESS, - AMDGPU::FlatVariant::FlatGlobal)) { + SIInstrFlags::FlatGlobal)) { Addr = PtrBase; ImmOffset = ConstOffset; } else { @@ -5967,7 +5966,7 @@ AMDGPUInstructionSelector::selectGlobalSAddr(MachineOperand &Root, if (NeedIOffset) { std::tie(SplitImmOffset, RemainderOffset) = TII.splitFlatOffset(ConstOffset, AMDGPUAS::GLOBAL_ADDRESS, - AMDGPU::FlatVariant::FlatGlobal); + SIInstrFlags::FlatGlobal); } if (Subtarget->hasSignedGVSOffset() ? isInt<32>(RemainderOffset) @@ -6155,7 +6154,7 @@ AMDGPUInstructionSelector::selectScratchSAddr(MachineOperand &Root) const { if (ConstOffset != 0 && isFlatScratchBaseLegal(Addr) && TII.isLegalFLATOffset(ConstOffset, AMDGPUAS::PRIVATE_ADDRESS, - AMDGPU::FlatVariant::FlatScratch)) { + SIInstrFlags::FlatScratch)) { Addr = PtrBase; ImmOffset = ConstOffset; } @@ -6233,7 +6232,7 @@ AMDGPUInstructionSelector::selectScratchSVAddr(MachineOperand &Root) const { Register OrigAddr = Addr; if (ConstOffset != 0 && TII.isLegalFLATOffset(ConstOffset, AMDGPUAS::PRIVATE_ADDRESS, - AMDGPU::FlatVariant::FlatScratch)) { + SIInstrFlags::FlatScratch)) { Addr = PtrBase; ImmOffset = ConstOffset; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h index b56280e025fa1..7a7a688262934 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h @@ -247,9 +247,8 @@ class AMDGPUInstructionSelector final : public InstructionSelector { InstructionSelector::ComplexRendererFns selectSmrdSgprImm(MachineOperand &Root) const; - std::pair<Register, int> - selectFlatOffsetImpl(MachineOperand &Root, - AMDGPU::FlatVariant FlatVariant) const; + std::pair<Register, int> selectFlatOffsetImpl(MachineOperand &Root, + uint64_t FlatVariant) const; InstructionSelector::ComplexRendererFns selectFlatOffset(MachineOperand &Root) const; diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h index d6120ee3c33d2..9867f5b02d7a7 100644 --- a/llvm/lib/Target/AMDGPU/SIDefines.h +++ b/llvm/lib/Target/AMDGPU/SIDefines.h @@ -198,11 +198,6 @@ enum ClassFlags : unsigned { } namespace AMDGPU { - -// Identifies which FLAT address-space segment an instruction operates on. -// Passed to helpers like isLegalFLATOffset / splitFlatOffset. -enum class FlatVariant : unsigned { FLAT, FlatGlobal, FlatScratch }; - enum OperandType : unsigned { /// Operands with register, 32-bit, or 64-bit immediate OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET, diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp index ac4a6f1011668..fac746a6a7d16 100644 --- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp @@ -2232,7 +2232,7 @@ bool SIFrameLowering::allocateScavengingFrameIndexesNearIncomingSP( // on frames with alignment requirements. if (ST.hasFlatScratchEnabled()) { if (TII->isLegalFLATOffset(MaxOffset, AMDGPUAS::PRIVATE_ADDRESS, - AMDGPU::FlatVariant::FlatScratch)) + SIInstrFlags::FlatScratch)) return false; } else { if (TII->isLegalMUBUFImmOffset(MaxOffset)) diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index a730e06721f47..e35a7bf4e4a16 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -1914,11 +1914,10 @@ bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM, return AM.BaseOffs == 0 && AM.Scale == 0; } - using AMDGPU::FlatVariant; - FlatVariant FlatVariant = - AddrSpace == AMDGPUAS::GLOBAL_ADDRESS ? FlatVariant::FlatGlobal - : AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ? FlatVariant::FlatScratch - : FlatVariant::FLAT; + decltype(SIInstrFlags::FLAT) FlatVariant = + AddrSpace == AMDGPUAS::GLOBAL_ADDRESS ? SIInstrFlags::FlatGlobal + : AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ? SIInstrFlags::FlatScratch + : SIInstrFlags::FLAT; return AM.Scale == 0 && (AM.BaseOffs == 0 || Subtarget->getInstrInfo()->isLegalFLATOffset( diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 1a969b2b3a877..2333d2906552f 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -10421,19 +10421,18 @@ bool SIInstrInfo::splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, // This function ignores the addressing mode, so if an offset cannot be used in // one addressing mode, it is considered illegal. bool SIInstrInfo::isLegalFLATOffset(int64_t Offset, unsigned AddrSpace, - AMDGPU::FlatVariant FlatVariant) const { + uint64_t FlatVariant) const { // TODO: Should 0 be special cased? if (!ST.hasFlatInstOffsets()) return false; - using AMDGPU::FlatVariant; - if (ST.hasFlatSegmentOffsetBug() && FlatVariant == FlatVariant::FLAT && + if (ST.hasFlatSegmentOffsetBug() && FlatVariant == SIInstrFlags::FLAT && (AddrSpace == AMDGPUAS::FLAT_ADDRESS || AddrSpace == AMDGPUAS::GLOBAL_ADDRESS)) return false; if (ST.hasNegativeUnalignedScratchOffsetBug() && - FlatVariant == FlatVariant::FlatScratch && Offset < 0 && + FlatVariant == SIInstrFlags::FlatScratch && Offset < 0 && (Offset % 4) != 0) { return false; } @@ -10446,7 +10445,7 @@ bool SIInstrInfo::isLegalFLATOffset(int64_t Offset, unsigned AddrSpace, // See comment on SIInstrInfo::isLegalFLATOffset for what is legal and what not. std::pair<int64_t, int64_t> SIInstrInfo::splitFlatOffset(int64_t COffsetVal, unsigned AddrSpace, - AMDGPU::FlatVariant FlatVariant) const { + uint64_t FlatVariant) const { int64_t RemainderOffset = COffsetVal; int64_t ImmField = 0; @@ -10460,7 +10459,7 @@ SIInstrInfo::splitFlatOffset(int64_t COffsetVal, unsigned AddrSpace, ImmField = COffsetVal - RemainderOffset; if (ST.hasNegativeUnalignedScratchOffsetBug() && - FlatVariant == AMDGPU::FlatVariant::FlatScratch && ImmField < 0 && + FlatVariant == SIInstrFlags::FlatScratch && ImmField < 0 && (ImmField % 4) != 0) { // Make ImmField a multiple of 4 RemainderOffset += ImmField % 4; @@ -10476,13 +10475,12 @@ SIInstrInfo::splitFlatOffset(int64_t COffsetVal, unsigned AddrSpace, return {ImmField, RemainderOffset}; } -bool SIInstrInfo::allowNegativeFlatOffset( - AMDGPU::FlatVariant FlatVariant) const { +bool SIInstrInfo::allowNegativeFlatOffset(uint64_t FlatVariant) const { if (ST.hasNegativeScratchOffsetBug() && - FlatVariant == AMDGPU::FlatVariant::FlatScratch) + FlatVariant == SIInstrFlags::FlatScratch) return false; - return FlatVariant != AMDGPU::FlatVariant::FLAT || AMDGPU::isGFX12Plus(ST); + return FlatVariant != SIInstrFlags::FLAT || AMDGPU::isGFX12Plus(ST); } static unsigned subtargetEncodingFamily(const GCNSubtarget &ST) { diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h index 558607b863d68..f5658021df954 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -1713,16 +1713,16 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo { /// Returns if \p Offset is legal for the subtarget as the offset to a FLAT /// encoded instruction with the given \p FlatVariant. bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace, - AMDGPU::FlatVariant FlatVariant) const; + uint64_t FlatVariant) const; /// Split \p COffsetVal into {immediate offset field, remainder offset} /// values. - std::pair<int64_t, int64_t> - splitFlatOffset(int64_t COffsetVal, unsigned AddrSpace, - AMDGPU::FlatVariant FlatVariant) const; + std::pair<int64_t, int64_t> splitFlatOffset(int64_t COffsetVal, + unsigned AddrSpace, + uint64_t FlatVariant) const; /// Returns true if negative offsets are allowed for the given \p FlatVariant. - bool allowNegativeFlatOffset(AMDGPU::FlatVariant FlatVariant) const; + bool allowNegativeFlatOffset(uint64_t FlatVariant) const; /// \brief Return a target-specific opcode if Opcode is a pseudo instruction. /// Return -1 if the target-specific opcode for the pseudo instruction does diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp index c060e53577221..2a854312d6125 100644 --- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp +++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp @@ -2410,9 +2410,9 @@ bool SILoadStoreOptimizer::promoteConstantOffsetToImm( unsigned AS = SIInstrInfo::isFLATGlobal(MI) ? AMDGPUAS::GLOBAL_ADDRESS : AMDGPUAS::FLAT_ADDRESS; - AMDGPU::FlatVariant FlatVariant = AS == AMDGPUAS::GLOBAL_ADDRESS - ? AMDGPU::FlatVariant::FlatGlobal - : AMDGPU::FlatVariant::FLAT; + uint64_t FlatVariant = AS == AMDGPUAS::GLOBAL_ADDRESS + ? SIInstrFlags::FlatGlobal + : SIInstrFlags::FLAT; bool AllowNegativeOffset = TII->allowNegativeFlatOffset(FlatVariant) && !TII->usesASYNC_CNT(MI); // The async global instructions use i24 offset for global address but u16 diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index a783f824a8088..b2b58d4392085 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -911,7 +911,7 @@ bool SIRegisterInfo::needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { return !TII->isLegalMUBUFImmOffset(FullOffset); return !TII->isLegalFLATOffset(FullOffset, AMDGPUAS::PRIVATE_ADDRESS, - AMDGPU::FlatVariant::FlatScratch); + SIInstrFlags::FlatScratch); } Register SIRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, @@ -1077,7 +1077,7 @@ void SIRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, if (IsFlat) { assert(TII->isLegalFLATOffset(NewOffset, AMDGPUAS::PRIVATE_ADDRESS, - AMDGPU::FlatVariant::FlatScratch) && + SIInstrFlags::FlatScratch) && "offset should be legal"); FIOp->ChangeToRegister(BaseReg, false); OffsetOp->setImm(NewOffset); @@ -1120,7 +1120,7 @@ bool SIRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, return TII->isLegalMUBUFImmOffset(NewOffset); return TII->isLegalFLATOffset(NewOffset, AMDGPUAS::PRIVATE_ADDRESS, - AMDGPU::FlatVariant::FlatScratch); + SIInstrFlags::FlatScratch); } const TargetRegisterClass * @@ -1695,7 +1695,7 @@ void SIRegisterInfo::buildSpillLoadStore( bool IsOffsetLegal = IsFlat ? TII->isLegalFLATOffset(MaxOffset, AMDGPUAS::PRIVATE_ADDRESS, - AMDGPU::FlatVariant::FlatScratch) + SIInstrFlags::FlatScratch) : TII->isLegalMUBUFImmOffset(MaxOffset); if (!IsOffsetLegal || (IsFlat && !SOffset && !ST.hasFlatScratchSTMode())) { SOffset = MCRegister(); @@ -3145,7 +3145,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, TII->getNamedOperand(*MI, AMDGPU::OpName::offset); int64_t NewOffset = Offset + OffsetOp->getImm(); if (TII->isLegalFLATOffset(NewOffset, AMDGPUAS::PRIVATE_ADDRESS, - AMDGPU::FlatVariant::FlatScratch)) { + SIInstrFlags::FlatScratch)) { OffsetOp->setImm(NewOffset); if (FrameReg) return false; _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
